MINIMUM POWER SUPPLY FINFET DEVICE CIRCUIT INTERACTION

Abstract

Constant Field Scaling and Constant Voltage Scaling are two methods used for reducing the power consumption. Supply Voltage Scaling (i.e. Constant Field Scaling) is most effective method for controlling the power consumption in digital logic circuits. Every digital logic has some fundamental limit of supply voltage below which it cannot be operated. Several researchers have determined the fundamental power supply voltage for CMOS based digital logic circuits. It has been found that minimum supply voltage required for CMOS based inverter is 36mV. In the previous work, it has been calculated that near subthreshold operation of FinFET device shows more promising results than CMOS based devices and hence in recent past an analysis has been done to calculate the fundamental limit of power supply for FinFET based inverters and other logic circuits. For FinFET based inverter it comes out to be 28mV. It was entirely a theoretical approach that can be used to calculate the practical limit for operation of different logic circuits by considering the noise and other variability issues such as threshold variation temperature variation. Extending the work of minimum power supply required for in inverter, an analytical approach is being used to calculate the minimum power supply required for FinFET based pass transistor followed by latch circuit using previously developed subthreshold current equation for FinFET devices. In addition to this with the help of minimum power supply approach a six transistor SRAM cell is designed and a mathematical model of read noise margin (RSNM) is developed for six transistor SRAM cell with variability of no of fins and temperature. It has been found that read noise margin varies with number of fins for a particular supply voltage so sizing issues is very critical for noise margin in SRAM.