DESIGN OF NEXT GENERATION NON-VOLATILE MEMORIES

Abstract

CMOS technology has reached its scaling limit below 20nm technology node hence spintronics based devices came into existence which can be further scaled down and gives reliable performance. Spintronics is new technology which makes use of spin of an electron whileconventional electronic devices rely on the transport of electrical charge carrierelectrons in a semiconductor. Devices that depend on electrons spin form the foundation of spintronics also known as spintronics.Magnetic Random-Access Memory stores 0 or 1 depending on magnetic orientation of free layer and pinned layer of Magnetic Tunnel Junction. In this thesis we presented a comparison of Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) and Static Random-Access Memory (SRAM) caches. Here we demonstrated that STT-MRAM is one of a good candidateto replace SRAM from memory hierarchy of embedded systems, due to reduced leakage and higher density of MRAM. Gem5 full system mode is used along with NVSim and Splash2 benchmark suite for both ARM and x86 processors to explore L1 and L2 cache memory for calculating area, Static energy consumed, cache misses, cache hits, run time for both SRAM and MRAM caches and combination of both.Also created a benchmark in C++ which detects the edges of an image and used it for both ARM and x86 processors to explore L1 and L2 cache memory for calculating area, Static energy consumed, cache misses, cache hits, run time for MRAM only. Keywords: Spintronics, MRAM, SRAM, NVSim, Gem5, x86 Processor, ARM Processor, L1 Cache, L2 Cache, Memory Hierarchy, Splash2 Benchmark Suite, Edge detection of an image