RELIABILITY AWARE AND ENERGY EFFICIENT CIRCUIT DESIGN IN SUB NANOMETRE TECHNOLOGY

Abstract

As complimentary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometre range, a number of non idealities must be addressed for successful circuit design. Increased leakage current and secondary effects became serious obstacle to further scaling of planar devices. Apart from this, in deeply-scaled technologies, displacing a few atoms within transistors due to aging phenomena may endanger the functionality of the entire design. Designers have to add pessimistic timing margins to the circuits as guardbands to avoid timing violations within the expected lifetime. Under the above challenges and with the available resources, this dissertation work presents study/methodology/design that assist in designing reliable and energy efficient VLSI circuits in sub-nanometre technology node.  Resources Available for dissertation work  a. Standard cell libraries 45nm planar CMOS (initial library and degradation characterized library at 10 year lifetime) 16nm FinFET (initial library and degradation characterized library at 10 year lifetime) b. Tools available Synopsys Design Compiler (for logic synthesis), Questasim (for simulation/verification), Synopsys Primetime (for timing/power analysis), MATLAB (for Image Processing)  Challenges addressed/Work Completed  a. Energy Efficient Digital Circuit Design using FinFET Challenge: Increased leakage current becomes an obstacle for continued scaling ofplanar CMOS technology Solution: FinFET as a new transistor type is widely accepted as a solution for energyefficiency and more control for gate on channel. In this work, performance comparison is done on the basis of complex circuits, between 16nm FinFET and 45nm planar MOSFET. An Image processing circuit is implemented for analysis. Along with this, benchmark circuits are used to back up the results. b. Reliability Aware logic synthesis for guardband optimization Challenge: Unfortunately, most of the current Electronic Design Automation (EDA)tools lack in the ability to accurately predict and analyze the impact of BTI. Pessimistic timing margins are added to the circuits as guardbands to avoid timing violations within the lifetime . Recent technology nodes operating under low supply ii voltages steadily narrow the available design space for these guardbands. Optimizing guardbands becomes a task that additionally needs to be considered. Solution: Propose aging aware logic synthesis approach for circuit design forachieving best frequency of operation possible. c. NBTI tolerant and Energy Efficient Time to Digital converter Challenge: Analog and Mixed signal circuits are not able to take the advantage ofscaling due to voltage based signal processing which results in low resolution. Solution: Migrating analog designs to digital designs are a solution for adapting thepace of scaling to analog/mixed-signal designs. Researchers try to step towards time based circuits which offer high resolution for mixed-signal circuits. Time to Digital converter is a core block in any Time based systems. In this work, a TDC architecture is proposed and implemented.