NEXT GENERATION TUNNEL FIELD EFFECT TRANSISTORS FOR DIGITAL APPLICATIONS

Abstract

As we are shrinking the dimensions of conventional devices like MOSFETs, various Short Channel E ects [ SCEs ] such as voltage roll-o , DIBL, mobility degradations are coming into picture. Also, the temperature a ects the subthreshold slope [SS] of the device. To reduce the power consumption scaling of the supply voltages to a lower value is advisable. The scaling of the devices leads to the need of novel devices to provide a better way to improve the technological development of the semiconductor industry. As per day to day requirement of high speed and low power devices lot of research work on scaling is carry out to achieving the required goal. Most important parameters to scale down are channel length, gate oxide thickness and supply voltage. In accordance with the ITRS Roadmap some new devices with di erent geometric structure like SOI MOSFETs, Double Gate FETs, Tri Gate FETs, Fin - FETs, Gate All Around FETs etc. are introduced. Fin FETs have better gate controllability as the gate have control from three sides of the channel.But, these devices su ers with the conventional limit on the sub-threshold slope. Tunnel Field E ect Transistor [ TFET ] is one of the alternative devices with its promising behavior of steep sub-threshold slope and lower leakage current. It has been proposed as a complement for the applications where low standby power dissipation is required. TFETs are based on Band To Band Tunneling [ BTBT] where the electrons tunnels from the valence band of the source to the conduction band of the channel. The main advantage of the TFETs is that they are almost independent of SCEs and temperature. Chapter I focuses on the motivation behind the emerging devices such as TFETs. In this chapter we discuss about the conventional devices and their limitations. Chapter II focuses on Tunnel Field E ect Transistors [TFETs] as an upcoming tech- nology. It describes the basic structure of TFETs and their working principle. This chapter also explains the role of channel in the working of TFETs. The limitations of TFET as a device and various ways to mitigate the e ect of ambipolarity have also been discussed. This chapter also focuses on the di erent types of TFET structures like Dou- ble Gate TFETs, Double Gate Dual Material TFETs, Triple Metal Gate TFETs, Gate All Around TFETs, Doping Less TFETs which have been suggested in the literature to improve the ON current of the device with reduced OFF current. This chapter discusses in detail about the e ects of each structural change in the current of the device. Chapter III focuses on the comparison of the di erent TFETs structures in terms of iii the capacitances of the devices. The basic aim of this chapter is to compare and study their transient characteristics as an inverter. Chapter IV focuses on the novel TFET structure with stacked drain which can be used to reduce to the ambipolar current. Impact of various variations on device parameter have also been studied. The novelty of the proposed structure is that it does not a ect the level of the ON current. The measured sub-threshold slope of our proposed DGSD TFET is 30.1 mv/decade.