LOW VOLTAGE ANALOG CIRCUIT DESIGN TECHNIQUES IN FINFET TECHNOLOGIES

Abstract

Scaling of the planar MOSFET below the 22nm technology is not only facing difficulties but also it imposes certain limitations like short channel effects (SCEs), threshold voltage roll off and gate-induced drain leakage (GIDL) which results exponential increase in the leakage current. Thus FinFET’s are proposed as a solution for further scaling and the fabrication process of these structures and conventional transistors are also quite similar. In this dissertation, we analysed how the analog and device parameters of FinFET device like Transconductance, Output impedance, Intrinsic gain, Unity gain frequency, Electron velocity, Electron density and Gate capacitance are varying with the gate and drain bias voltages. Using FinFET device, the different amplifier circuits like differential amplifier with and without parallel stack gate, telescopic cascode amplifier with mirror connected load are designed and observed how the characteristics of gain and unity gain bandwidth are varying with the bias voltages of the tail transistor. In telescopic cascode amplifier simulations for various extension lengths near drain region of FinFET device are carried out and comparison of gain and UGB for various drain extension lengths are discussed. Using FinFET device differential amplifier with capacitive feedback and telescopic cascode amplifier with capacitive feedback are also designed and observed how the characteristics of gain and cut off frequency of these circuits are varying with two different feedback capacitance C1 and C2.