PERFORMANCE AND VARIABILITY ANALYSIS OF 6T SRAM CELL USING VERTICAL SILICON NANOWIRE

Abstract

In this dissertation, the Silicon Vertical Nanowire FET with asymmetry of source and drain region with respect to gate terminal (VNW-A) has been analyzed for digital circuit design (e.g. logic gate, SRAM cell). Due to asymmetricity, the VNW-A device has been configured as STP (source top of p-type), STN (source top n-type), SBN (source bottom ntype) and SBP (source bottom p-type). The well experimental and TCAD calibrated VNW-A FET Verilog-A compact model has been employed for SRAM cell analysis. The VNW-A transistor has been configured either as source top (ST) or source bottom (SB) with either p or n type. By this VNW-A device structure results in the formation of four SRAM cell design by considering conventional approach of PD (pull down) ≥ AX (access) > PU (pull up). All four designs were investigated for read and write static (read/write noise margin) and dynamic analysis (read/write access time) in the various 6T SRAM cell design configurations i.e. C_111, C_112, C_122 and C_123 where C_xyz denotes number of wires in PU, AX and PD transistor respectively. Out of all the designs and configurations, SRAM design in D1 (PU: STP, AX: STN, PD: SBN) with C_112 configuration performed better for WNM (write noise margin) and WAT (write access time). Similarly, design D2 (PU: SBP, AX: SBN, PD: SBN) with configuration C_112 performed the best for RNM (read noise margin) and RAT (read access time). Further, the VNW-A SRAM cell layout area advantage for different design and configuration have been analyzed and compared with other technology node. Finally it is concluded that the VNW-A SRAM cell stability can be improved by changing design without area penalty. At the last, my dissertation work of variability using VNW-A has also been carried out by varying channel length (Lg), oxide thickness (tox) ,radius (R) and combined variation of all these physical parameter in 6T SRAM cell. The above work demonstrated that the data of static voltage noise margin and write noise margin has varied within tolerable limits. Therefore, it is possible to fix the variable data. The VNW based basic logic gates (NAND, NOR and inverter) have also been discussed. Finally, the delay, energy, power consumption, energy delay product (EDP) and power delay product (PDP) have been analyzed and compared with the FinFETs based data