2.4 GHz SINUSOIDAL FREQUENCY SYNTHESIS

Abstract

The modern communication system requires a system which is susceptible to timing jitter and phase noise. The minimization of sources of timing error in the high levels of integration in many communication systems is still a challenging task. It mainly consists of a phase locked loop for timing recovery or frequency synthesis which further utilized in clock generation and data recovery. Fully monolithic, on-chip VCO and synthesizer design are in fully demand for high integration implementation. The ring and LC oscillator are an integral part of VCO. Ring oscillator is superior over LC oscillator in terms of easy integration, high tuning range and less area requirement in layout but it suffers with the poor phase noise. In this dissertation, our aim is to explore high-frequency (2.4GHz wireless band) generation in CMOS 180nm (SCL PDK) technology. We mainly focused on Integer-N frequency synthesizer along with its design challenges, limitation and motivation to use other architecture to reduce its periodic noise spurs. To minimize reference spurs, a spurs suppression technique is used along with the conventional Charge Pump Phase Locked Loop (CPPLL) architecture. To minimize the noise simulation time of closed loop PLL, a MATLAB simulation is performed. It is based on the phase relationship of all noise sources to output phase, for that an individual blocks Noise Transfer Function (NTF) is being carried out. To get the effect of individual noise sources, the PSS and PNoise data of each block is extracted from cadence Spectre. Further by increasing the loop bandwidth lock time will decrease but the spur level will increase hence the Frequency synthesizer loop filter and phase frequency detector are designed accordingly to fit both of the trade off so that it will give optimum performance for specific application requirement. A spur reduction technique is used to bypass the trades off in locked conditions. In this technique the periodic changes in the control voltage in every reference cycle is controlled by using the randomized clock signal. That clock signals is generated by using a Pseudo Random Bit Stream generator (PRBS). By using this method the power at the spur frequency is spread over the entire frequency range. The post layout simulation is done in cadence caliber view. The spurs magnitude is reduced by around 8-10dB and the phase noise of PLL is around -89dBc/Hz. The overall power consumption is around 4.84 mW and FOM of -218 dB. Also the area consumed by the PLL is around 192*184 μ𝑚2.