1. Shodhbhagirathi @ IITR
  2. ELECTRONICS AND COMMUNICATION ENGINEERING (FORMERLY ELECTRONICS & COMPUTER ENGINEERING)
  3. DOCTORAL THESES (E & C)
Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/157
Full metadata record
DC FieldValueLanguage
dc.contributor.authorJain, N.C.-
dc.date.accessioned2014-09-11T06:41:48Z-
dc.date.available2014-09-11T06:41:48Z-
dc.date.issued1968-
dc.identifierPh.Den_US
dc.identifier.urihttp://hdl.handle.net/123456789/157-
dc.guideLal, M.-
dc.language.isoenen_US
dc.subjectREALIZATION OF RESISTIVEen_US
dc.subjectPORT NETWORKSen_US
dc.subjectCUT-SET MATRICES,en_US
dc.subjectLOOP, MATRICESen_US
dc.titleREALIZATION OF RESISTIVE n-PORT NETWORKS, CUT-SET MATRICES, AND LOOP, MATRICESen_US
dc.typeDoctoral Thesisen_US
dc.accession.number105555en_US
Appears in Collections:DOCTORAL THESES (E & C)

Files in This Item:
File Description SizeFormat 
REALIZATION OF RESISTIVE n-PORT NETWORKS, CUT-SET MATRICES, AND LOOP MATRICES.pdf28.42 MBAdobe PDFView/Open
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.