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dc.contributor.authorKaushlendra, Kumar-
dc.date.accessioned2023-07-14T11:56:41Z-
dc.date.available2023-07-14T11:56:41Z-
dc.date.issued2019-06-
dc.identifier.urihttp://localhost:8081/xmlui/handle/123456789/15577-
dc.description.abstractNAND Flash memory is a non-volatile memory and has various applications such as memory card, flash card, digital camera, etc. It is developed from electrically erasable programmable read-only memory (EEPROM). The basic mechanism of NAND Flash memory is to store the electrical charge in the floating gate by applying voltage on the control gate/substrate. The stored charges in the floating gate change the threshold voltage of the memory device and change in threshold voltage is related to programmed/erased state of NAND Flash memory. We reported a detailed analysis of 2D/3D NAND Flash memory with variation in different parameters such as contact resistance, metal work function, source/drain and channel doping, channel length, trap density. These variations are implemented in three devices: planar 2D NAND Flash memory, 3D NAND Flash memory, and vertical cylindrical semiconductor oxide silicon nitride oxide semiconductor (SONOS) cell with bilayer polysilicon channel. The simulation setup is well calibrated with the experimental results of the highly scaled vertical cylindrical SONOS cell with bilayer polysilicon channel implemented in 3D NAND memory. The effect of trap density and channel length variation on the memory window and threshold voltage of programmed/erased state are also studied and explained in detail. The effect of contact resistance, metal work function, channel doping, and source/drain doping are studied for three different device structures. We also investigated the effect of crystalline channel and polysilicon channel on memory window. In this study, MONOS/SONOS devices are analysed during programmed/erased state and the memory window is calculated. Further, the impact of electron/hole trapping (floating gate) on the memory window is investigated. As contact resistance of source/drain, and gate increases, threshold voltage increases in 2D/3D NAND flash memory, and as we increase the trap density then memory window also increases in 3D NAND flash memory. Finally, the dissertation presents variability of SONOS (Semiconductor Oxide Silicon Nitride Oxide Semiconductor) type NAND Flash Memory, which by studying the variation of device parameters like channel length, trap density, polysilicon channel thicknessen_US
dc.description.sponsorshipINDIAN INSTITUTE OF TECHNOLOGY ROORKEEen_US
dc.language.isoenen_US
dc.publisherI I T ROORKEEen_US
dc.subjectFlash Memory- FMen_US
dc.subjectFloating Gate – FGen_US
dc.subjectTunnel Oxide-TOXen_US
dc.subjectBlocking Oxide- BOXen_US
dc.titleNAND FLASH MEMORYen_US
dc.typeOtheren_US
Appears in Collections:MASTERS' THESES (Physics)

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