Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/15348
Authors: Prakash, Om
Keywords: Silicon Nanowire;Inverter;Bias Temperature Instability;Circuit Topology
Issue Date: Apr-2019
Publisher: I.I.T Roorkee
Abstract: Silicon nanowire (SiNW) FET is one of the most promising candidates at extremely scaled technology nodes due to its superior channel controllability and CMOS compatibility. An accurate physics-based compact model is necessary for process and circuit design engineer to predict the available silicon data for highly scaled dimensions. Moreover, the model can also be used to accelerate the device-circuit co-optimization, which will reduce the fabrication cost and development cycle at the starting phase of future technology. In this study, we develop a unified Verilog-A compact model for lateral SiNW FET circuit design and analysis. The compact model incorporates important nanoscale effects as well as the geometry-dependent parasitic capacitances and resistance models. The parasitic models are scalable and TCAD calibrated. The Verilog-A model is calibrated to accurately match with reported experimental and TCAD based single & multiwire SiNW FET I-V and C-V characteristics. We have designed SiNW FET based basic core logic gates such as INVERTER, NAND, NOR, Buffer, XOR, XNOR and analyzed their performance. It is seen that the SiNW CMOS based logic gates have better power dissipation (~3-4X), energy-delay product (~2-3X), and power delay product (~3X) compared to corresponding FinFET based designs. Further, we have examined stability metrics (e.g., read, write noise margins and access time), geometrical variability, and layout area optimization of SiNW FET based 6T SRAM employing multiwire sizing technique. The different NW SRAM design configurations (e.g., C_111, C_123, etc., where C_111 denotes the number of wires in pull up (PU), access (ACC), and pull down (PD) transistors respectively) are investigated. Among all design configurations, C_112 is found to be the best configuration considering overall performances such as write stability, speed, layout area, and variability tolerance. Bias temperature instability (BTI) is one of the major reliability concern at nanoscale nodes and requires an accurate model to predict device and circuit performance. BTI includes negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), which occurs on p and n-type SiNW FET devices respectively. The stress and recovery BTI model for Si NW FET is obtained from the experimental SiNW FETs using a range of stress voltage, time, and temperature. Thereafter, the developed Verilog-A compact model is integrated with ii the BTI model for nanowire (NW) CMOS circuit simulation and design. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of a lifetime) due to fast trapping, inverter delay, and RO frequency degrade rapidly and saturates in long-term 10-year lifetime. Further, the combined impact of NBTI and PBTI are analyzed in circuits and a method is proposed to mitigate their impact. We demonstrated that the delay degradation is circuit topology dependent in which series-connected transistors are more prone to degradation due to PBTI (NBTI) in NAND (NOR) gates. Finally, the design of SRAM cell employing multi-wire sizing technique is investigated. It is found that the SRAM cell design margins are configuration dependent in which impact of BTI degrades the RNM by 15 % - 30 % and WNM improves by 5 % - 8 % for 10-year lifetime. We show that the BTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores the need for mitigating BTI degradation in NW CMOS, both at the device and circuit level. Finally, the combined impact of time zero variability and BTI reliability on the core logic gates and read/write stability of the 6T SRAM cell is investigated. We found that the combined impact of time zero variability and BTI reliability degrades the mean and sigma value of circuit delay and SRAM RNM stability. We propose a method to minimize degradation under the influence of variability and reliability by selecting appropriate NW FET design configuration. It is found that overall the C_112 is the best SRAM cell design configuration, having higher read/write reliability and variability tolerance. The comprehensive predictive model framework presented here is a valuable tool for variability and reliability-aware SiNW CMOS circuit design and analysis. The results and developed model of SiNW FET presented in this thesis are important benchmarks for the future studies in SiNW CMOS circuit design.
URI: http://localhost:8081/xmlui/handle/123456789/15348
Research Supervisor/ Guide: Manhas, S. K.
metadata.dc.type: Thesis
Appears in Collections:DOCTORAL THESES (E & C)

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