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|Title:||DESIGN AND ANALYSIS OF NEAR THRESHOLD CMOS STORAGE ELEMENTS CONSIDERING VARIATIONS AND SOFT ERRORS|
|Authors:||Kumar, Chaudhry Indra|
|Keywords:||Energy Efficient Computation;Voltage and Temperature;Radiation Hardened Latches;Significant Energy Savings|
|Abstract:||Energy efficient computation is vital for the success of the next generation very large scale integration (VLSI) applications. Operating circuits in sub/near-threshold voltage (NTV) regime is one of the techniques to design energy efficient circuits. However, NTV computing has created resiliency challenges, including increasing timing faults due to process, voltage and temperature (PVT) variations and data-retention failures due to radiation-induced soft errors in modern digital circuits. To address these issues resilient circuit techniques are used to mitigate the performance degradation and data failures resulting from PVT variations and external transient noise. The work in this thesis proposes a framework to handle timing errors and soft errors issues in the NTV regime employing a resilient approach. First, we proposed a resilient latch that overcomes the timing errors issues in the NTV region. Moreover, a systematic methodology to resolve soft error issues, which are critical for memory elements (latches/SRAM) in the NTV is developed. For the same, first, an accurate model to estimate the critical charge for a static D latch is derived. Using the proposed model, soft error susceptible latches/Flip-Flop’s can be identified at an initial design stage (pre-layout) and, subsequently, replaced by the radiation hardened latches. However, the reported radiation hardened latches are implemented with too large cost penalties in terms of delay, power, and area. To overcome the issue, we proposed low cost and highly reliable radiation hardened latches in the NTV regime. In this thesis we also proposed a cost effective radiation hardened SRAM cell since it is similar to a static latch. In this thesis, first we present an energy efficient and resilient circuit design approach using novel self correcting latches (SCL). The proposed SCL technique corrects the faults due to timing violation caused by variations in data-paths and sequential elements automatically, thereby lowering PVT variation induced performance degradation. Our SCL technique employs inverse narrow width effect (INWE) in designing the self-correcting latches to reduce performance variability. The SCL technique can achieve higher performance when compared to reported resilient techniques with a much smaller area and power overhead. Consequently, most of the traditional design margins due to global and local PVT variations are eliminated which results in significant energy savings. ii Further, we propose a physics based semi-analytical model to estimate the critical charge, which is a key to assessing the radiation-induced soft error susceptibility of static D-latch. To develop the model, first, we argue that the value of the critical charge increases with fan-out load of a latch. The proposed model is a function of design parameters such as transistor sizes, supply voltage and fan-out load. Consequently, it enables characterizing the spread of critical charge due to process-induced variations in these parameters. This can help circuit designers to estimate and optimize the critical charge and hence the SER at an initial design stage. The critical charge estimated by the model is in good agreement with SPECTRE simulations. Therefore, the proposed model can serve as a reliable alternative to time-intensive SPICE simulations for estimating the critical charge at design stage. In order to limit the radiation-induced soft errors further, we propose three novel highly reliable energy efficient radiation hardened latches. The proposed latches provide the soft error tolerance by using restorer circuits (RC) to hold the correct state and Muller C-element to block the fault. The RCs are based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better radiation tolerance. Furthermore, to improve the D-Q and CLK-Q transmission delay, we use INWE at the layout level of the proposed latches. The proposed latches effectively, maintain their soft error tolerance in the presence of PVT variations. We also verify the soft error rubostness of the proposed latches in TCAD mixed mode simulations. Finally, we extend our analysis to SRAM cells. Scaling of CMOS SRAM have led to a denser packing, however, this makes SRAM cells more susceptible to a single event multiple-node upset (SEMNU). Therefore, to mitigate the effect of SEMNU in SRAM cells, we propose novel energy efficient radiation hardened memory cells in NTV regime. The proposed cells maintain its radiation-induced soft error tolerance in the presence of PVT variations. The TCAD mixed mode simulations show that our memory cells have a better performace as compared to the existing radiation hardened memory cells. Therefore, for NTV and aerospace applications our proposed memory cells would be a better choice.|
|Research Supervisor/ Guide:||Bulusu, Anand|
|Appears in Collections:||DOCTORAL THESES (E & C)|
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