FPGA PROTOTYPING FOR MICROGRID PROTECTION

Abstract

The recent advancement of digital technology is the re-configurable hardware i.e. field programmable gate array (FPGA), programmed by Hardware Description Language (HDL) is used for high-speed applications. It has credentials for developing intelligent electronic devices, which are used in the power system components, and smart grid applications i.e. fast relay for the protection of the microgrid (MG) asking high computational demand, low latencies, reconfigurability, high bandwidth and parallel processing. Some inherent benefit of the FPGA device is the parallelism of hardware that increases the execution speed compared to sequential software architecture based technologies (μP and μC). Due to these predominant features, the FPGA based digital relays are being considered for the protection of MGs. MGs provides a platform for integration of various distributed generators (DGs) and renewable energy sources (RESs) like solar PVs and wind generators, loads and storage devices. These DGs and RESs serve multiple purposes viz. reducing the carbon footprint from the environment, reachability to remote demand locations, quick installation and low-cost maintenance etc. The MG is usually connected to the utility grid through a single bus called the point of common coupling (PCC) and hence, is capable of operating both in synchronism with the utility grid known as grid-connected mode and as an autonomous power island i.e. standalone mode. The small-scale MGs provide uninterrupted power supply to the end user during the period of power outages, emergencies and failures of the utility grid due to any abnormality or a fault occurring in the utility grid. There are several challenges for reliable operation of a MG in the field of monitoring, controls, and protection. Among these, the device development for the protection of the MG has been addressed in the present work. The existing overcurrent protection relays (OCRs) developed for passive distribution networks (radial network) are not applicable for active distribution networks viz. Microgrid (MG). Since the integrated distributed energy resources (DERs) are connected through power electronic interfacing (PEI) having fast dynamics, therefore, the MG is a low-inertial system. To overcome the stated problem, a fast relay is required for the protection of MG that can isolate the faulty section, detect its mode of operation and adapt threshold settings as per the operating mode. Protective hardware is required to be developed that can sense the faster dynamics within MG and also have the feature of parallel processing by which the computation time for decision making is reduced. The FPGA is such an electronic device that is used in the power system viii industry and smart grid applications asking for high computational demand, low latencies, reconfigurability and parallel processing. Due to these predominant features, the FPGA based digital relays are being considered for the protection of the MGs. In the present work, the FPGA based prototyping has been used for different block of OCR viz. DC-offset module, antialiasing filter, DFT filter module, harmonic detection module and relay emulation module are implemented with a higher degree of accuracy at low cost. Conventional OCRs are mostly used for the protection of the radial distribution network. However, in case of microgrid protection, OCRs maloperate due to the bidirectional power flow, the need of directional feature of the relay has become necessary. Therefore, the directional feature is added to the developed OCR prototype. Here, a digital phase detection module has been developed for the estimation of direction of current flowing through the power system network using a zero-crossing detector. A parallel architecture for phase and tripping time computation has been used in the proposed design that makes the developed relay faster by reducing the computation time of the algorithm. Here also, performance of the DOCR is tested by creating the faults at different locations with different values of time dial settings and plug-point-multiplier. Hardware-in-loop (HIL) verification of the relay is carried out with the real-time-digital simulator (RTDS) with FPGA prototype. The results are compared with the standard DOCR of the RTDS which verify the successful operation of the designed relay under different fault conditions. Islanding is the condition, which occurs when a portion of the distribution network (or MG) is disconnected from the utility grid and operates independently with the help of local DGs and RESs. Generally, two types of MG islanding occur i.e. intentional and unintentional. The intentional islanding is mainly performed to carry out some maintenance works within the MG and for the safety of the working personnel; whereas the unintentional islanding occurs due to the utility grid blackout by equipment failure, natural disaster or any abnormality in the power system. As per the suggested standard viz. UL-1741, IEC-62116 and IEEE 1547TM islanding must be detected and the active DGs are isolated from the MG within 2-seconds after detecting the islanding. Hence, it is an essential requirement to develop a fast relay that can detect the islanding (by sensing variation in parameters) within the stipulated time interval as well as take necessary action i.e. either isolate the affected section/DG of the MG (with non-critical loads) by generating the trip signal. In present work, the FPGA prototype for islanding detection based on the islanding discrimination factor (IDF) using the periodic maxima of superimposed voltage components is developed. A modular design approach is used to implement the islanding ix detection technique (IDT) algorithm. Verilog HDL has been used to optimize the hardware resources and minimize computational complexity. HIL verification of the IDT has been performed for islanding and non-islanding events with a microgrid test system developed on RTDS. The performance of the prototype has been verified under various test cases viz. for both islanding and non-islanding events. Now, the magnitude of a fault current depends on the operating mode of the MG as well as number and types of the integrated DGs placed within the MG. The contribution of the fault current by rotating machine-based sources is higher than that of PEI DERs as compared to their respective normal rated current. The magnitude of fault current is 6.0-10.0 p.u in the rotating machine whereas its magnitude is lower i.e. up to 1.0-2.0 p.u in case of PEI interfaced DERs. However, in the grid-connected mode of operation, the magnitude of fault current is greater than the magnitude of the fault current in the islanded mode of operation. Also, the trip time is more in the case of a standalone mode in comparison with the grid-connected mode. Hence, mode-adaptability of the OCR is inevitably required for the reliable operation of MG, which can be performed by changing the threshold setting i.e. pick-up current (Ip) setting of the OCR. In this work, a hardcore reconfigurable multifunctional relay is designed, which is used for the detection of operating modes of the MG as well as mode adaptation within the MG. Some additional functional modules viz. voltage unbalance module, rate of change of frequency (ROCOF) module and a soft controller are designed on the FPGA and added in the developed OCR prototype. HIL verification of the developed prototype is performed with the RTDS under various test conditions viz. under different power mismatches. Lastly, the prototype of a communication assisted adaptive relay (CAAR) is developed by adding a communication feature with the designed OCR to achieve mode adaptability of the relay installed at various DG located remotely. The status of these modes and the working status of the DGs are communicated through the wireless network. Here nRF24L01 wireless modules are used as the transmitter and the receiver of the CAAR. Performances of the CAAR prototype has been verified in HIL on a MG test system under the environment of RTDS. Different test cases i.e. operating modes of the MG, faults at different locations, types of faults and relay coordination are tested to validate the functionality of the developed prototype of CAAR. In the present work, the FPGA based prototype of the overcurrent relay (OCR) with its internal components viz. DC-offset module, anti-aliasing filter, DFT module, harmonic detection module and relay emulation module are developed with a higher degree of accuracy and low cost. Here, Verilog HDL is used to optimize the hardware resources and minimize x computational complexity. Furthermore, the directional feature is added to the developed OCR prototype, which is works as directional-OCR. Here, a digital phase detection module is used for the estimation of the direction of current by a zero-crossing detector. Performance of the relay is tested by creating the faults at different locations with different values of time dial settings and plug-point-multiplier.