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dc.contributor.authorTyagi, Tushar-
dc.date.accessioned2021-11-23T06:26:51Z-
dc.date.available2021-11-23T06:26:51Z-
dc.date.issued2019-06-
dc.identifier.urihttp://localhost:8081/xmlui/handle/123456789/15175-
dc.guideSumathi, P.-
dc.description.abstractThe present research work aims to propose a capacitance measurement system based on frequency estimation technique. The frequency estimation is performed using a frequency locked loop (FLL) based on moving window discrete Fourier transform (MWDFT) filter. The frequency estimation technique is able to accurately estimate the frequency when the input signal is non-sinusoidal. Further, it fulfills the following requirements: (i) provide wider frequency estimation range (ii) good accuracy (iii) less convergence time (iv) good frequency resolution (v) good slew rate (vi) ease of digital implementation. The various capacitance measurement techniques are reviewed. Due to the advantages of the C-F technique over the other methods special emphasis is laid to this method. For this purpose the existing sinusoidal frequency estimation techniques are reviewed and the possibility of applying them for capacitance measurement is explored. The relaxation oscillator is the most commonly used circuit for converting the capacitance in to the equivalent frequency. Since the output of the oscillator is a square wave, a square to sine wave conversion is required. The sinusoidal frequency estimation techniques are later applied to the input sine wave to estimate the frequency and thereby obtaining the accurate measurement of capacitance. However, most of the existing frequency estimation techniques could estimate the input frequency directly from the input square wave signal. The different frequency estimation techniques are categorized as: Phase locked loop (PLL), Frequency locked loop (FLL), Parameter estimation techniques and Discrete Fourier transform based frequency locked loop (DFT-FLL). A relaxation oscillator is simulated in MATLAB/Simulink environment using the simscape library with the specifications of the AD711 operational amplifier. The various frequency estimation techniques are also simulated. The output of the oscillator is fed to the different techniques and their performance is evaluated for center frequency and step change in frequency. The techniques are compared in terms of convergence time, accuracy, estimated frequency range and the capacitance measurement range. Further, the uncertainty analysis of the analog front end is performed. The performance of the frequency estimation techniques is evaluated in noisy environment and the effect of parasitic capacitances is analyzed by considering the practical model of capacitance sensor and op-amp. Further, a frequency estimation technique is proposed with fractional bin-index based movi ing window discrete Fourier transform (MWDFT). In order to increase the range of frequency estimation, different MWDFTs with bin-indices k = 0.5, 1, 1.5, 2 and 2.5 are chosen and incorporated in the frequency estimator. The structure of the MWDFT is modified with the positive feed-forward coefficients for fractional bin-indices and negative coefficients for integer multiples. The frequency of the input signal is estimated by adaptively adjusting the sampling pulses for MWDFT with integer and fractional bin-indices. The different MWDFT bins are appended in parallel with only one MWDFT bin connected to sampling pulse adjustment (SPA) at a time. The input signal is passed through the selector module which provides a coarse frequency estimation and decides the select line to choose the appropriate MWDFT bin. The experimental validation is performed by designing a relaxation oscillator using AD711 op-amp and center frequency of 20 kHz. The output of the oscillator is amplitude limited to 2 V and fed to ADC of the data conversion high speed mezzanine card. The data conversion card is connected to the Stratix III FPGA board with FPGA chip EP3SL150F1152C2N through HSMC port connector. The proposed scheme is designed in MATLAB/Simulink DSP builder for a center frequency of 20 kHz and then converted to VHDL code with the help of Quartus II synthesizer to program the FPGA. When the capacitance under measurement changes, there is a corresponding change in the frequency of the oscillator output. The proposed technique generates the in-phase and quadrature signals. The quadrature signal is used by the SPA to correct for the frequency error in the FLL output. Therefore, the proposed technique is able to track the changes in frequency caused by a corresponding change in capacitance. The proposed work further explores the other available computationally efficient DFT structures for designing the FLL in order to improve the accuracy while reducing the computational burden. The proposed scheme employs the technique of quadrature signal generation (QSG) to generate the in-phase and quadrature components of the input signal. The quadrature signal is used to correct the frequency error under the varying input signal frequency. The proposed scheme shows good accuracy, consumes less resources and provides wider frequency operating range with less convergence time. To further reduce the number of frequency bins and increase the range of measurement, the modification in the structure of the MWDFT is introduced so that the frequency bin resoluii tion increases. The conventional structure of a MWDFT filter consists of a comb filter with negative feed-forward coefficient connected in cascade with a resonator. The feed-forward coefficient of the comb filter is changed to positive and number of delay elements is adjusted to obtain the necessary pole-zero cancellation. This unique property of MWDFT with finer granularity bin-indices is exploited to extract frequencies of finer resolution. A frequency locked loop is designed with MWDFT of finer granularity bins to estimate the frequency change of finer resolution. The proposed method is applied for capacitance measurement and the scheme is implemented on FPGA. The method is able to provide improved accuracy (0.05%), wider frequency estimation range (3.6 - 128 kHz), and wider capacitance measurement range (88.778 - 3156.565 pF). The proposed technique is tested for two variable sensing with finer granularity bins. Both the variable resistance and variable capacitance are incorporated in the oscillator circuit. Using switching operation only one of the measurand is connected to the circuit and the other is replaced with a fixed value of either resistance or capacitance. Additionally, to perform temperature measurement the resistance is replaced by a thermistor with positive temperature coefficient in the oscillator circuit. The method is able to measure a temperature of 40 - 92.6 C. Hence, the technique is able to provide a two variable sensing technique (resistance and capacitance) with wider measurement range.en_US
dc.description.sponsorshipIndian Institute of Technology Roorkeeen_US
dc.language.isoenen_US
dc.publisherI.I.T Roorkeeen_US
dc.subjectFrequency Locked Loop (FLL)en_US
dc.subjectMWDFTen_US
dc.subjectPhase Locked Loopen_US
dc.subjectWDFTen_US
dc.titleCAPACITANCE TO FREQUENCY CONVERSION BASED ON RECURSIVE DISCRETE FOURIER TRANSFORMen_US
dc.typeThesisen_US
dc.accession.numberG28727en_US
Appears in Collections:DOCTORAL THESES (Electrical Engg)

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