INVESTIGATION ON MULTI POINT CLAMPEDMULTILEVEL HIGH POWER FACTOR CONVERTERS

Abstract

AC-DC conversion of electric power is widely employed in various industrial applications. Traditionally, AC-DC converters, commonly known as rectifiers, are developed using diodes and thyristors to provide controlled, uncontrolled, unidirectional and bidirectional DC power. They suffer with the problems of poor power quality in terms of poor power factor at input terminals, injected current harmonics in power supply, resultant voltage distortion at point of common coupling due to line impedance, and rippled DC output at load end. To regulate power quality (PQ)issues, various guidelines such as IEEE 519, IEC 61000 for harmonic mitigation have been imposed. Filters such as passive filters, active filters, and hybrid filters along with conventional rectifiers have been extensively developed, especially in large rating and already existing installations. However, these filters are quite costly, bulky, and have substantial losses, which reduce overall efficiency of the complete system. In passive filters, the filtering characteristics are adversely affected with the source parameters and supply frequency. On the other hand, in some of the cases rating of converter used in active filters is almost close to the rating of load. Under such circumstances, it is better to use filtering within AC-DC conversion system. These converters called High Power Factor Converters (HPFCs) provide reduced size, high efficiency, controlled and regulated DC for the desired applications. The increasing trend for use of high power factor converters are more prominent in applications such as autonomous AC power systems, telecommunications, frontend converters for variable-speed drives, DC motor drive control and in many other applications where performance and power density are critical. Various configurations of HPFCs are proposed in the literature to improve power quality. These converters draw sinusoidal line currents with negligible total harmonic distortion at near unity input power factor. On the load-side, these converters provide regulated DC output voltage with reduced ripples. For low power applications, 3-phase, two level HPFCs may provide a cost effective solution. For medium voltage and high power applications, multi-pulse or multi-level converters are preferred. Muli tilevel HPFCs are now-a-days gaining wide popularity in many industrial applications because of their superior features such as, sinusoidal input current at unity power factor, lower value of dv=dt, reduced electro magnetic interference, high-quality DC output voltage with lower switching frequency and reduced filter size. Despite of having number of advantages, multi level converters (MLCs) with the increasing number of voltage levels, demand steep rise in power semiconductor devices (PSD) count and associated auxiliary circuits which include gate driver unit, protection circuit and heat sink. Therefore, hardware gets more complex, bulky and expensive. Further, this will reduce system reliability and ease of fault identification under abnormal operating conditions. Therefore, prime concern is to reduce PSD count and gate driver circuits along with voltage stress across devices. Very little work has been done to address these aspects. Therefore, the work is being carried out to address the above issues in MLC topologies. Instead of various multilevel topological structures, in this thesis a special emphasis is given to multi point clamped (MPC) topologies. In the present work, a comprehensive literature survey on MPC converter topologies is carried out. The topological parameters considered for comparison are number of controlled switches, additional clamping devices, driver circuits, gating signals, blocking voltage rating of controlled as well as uncontrolled switches and requirement of special devices like bidirectional switches. In addition, the performance parameters like device losses and converter efficiency, cost analysis and suitability of a topology for an application are also investigated. Based on investigations of existing topologies, a new three-phase three-leg multi-point clamped multilevel topology (3P-3L-MPC-MLT) is proposed. The proposed converter can be modulated similar to conventional MPC converters (diode clamped converter topology) with out additional clamping diodes and bidirectional switches to clamp the different voltage terminals of common DC link. Generalized N level formulation is derived in terms of above mentioned topological parameters and compared with counterpart topologies. Mathematical model of the proposed converter is developed for detailed analysis. A systematic design procedure is developed for selection of various power and control ii circuit parameters. Further, switching losses, conduction losses, efficiency and cost of the converter are estimated and compared with other MPC topologies. An attempt is made to reduce the device count further by removing one of the phase arms of 3P-3L-MPC-MLT. The derived multi point clamped multi level topology (3P-2L-MPC-MLT) is structured with two arms and remaining circuitry elements are same as 3P-3L-MPC-MLT. Two phases are connected with two individual arms and third phase is connected to the mid point of dc link. Although, the 3P-2L-MPCMLT has reduced device count due to omission of one leg, the power quality of input line currents and their harmonic spectrum are almost similar to 3P-3L-MPCMLT. However, the DC link voltage ripple is significantly higher than 3P-3L-MPC-MLT. The DC voltage ripple problem can be addressed independently by suitable filter capacitor values. In addition, the output dc link voltage in 3P-2L-MPC-MLT is 1.732 times of the dc link voltage established with same grid conditions in 3P-3L-MPC-MLT. Therefore, the percentage ripples are not high in both the cases. Because of high boosting, the switch stress also increased by 1.732 times in 3P-2L-MPC-MLT. For medium voltage applications, 3P-2L-MPC-MLT is one of the best economical option, whereas for higher voltage and power rating applications, this may not be a good choice due to limited commercial availability of higher rating power semiconductor devices. The topology development, operating principle, mathematical formulation and comparative analysis are also presented in this work. Another topology, to reduce the switch count is developed by restricting 3P-3LMPC- MLT to unidirectional applications. Three phase multi point clamped multilevel unidirectional topology (3P-3L-MPC-MLUT) is derived from 3P-3L-MPC-MLT by replacing some of the controlled switches (IGBTs) with uncontrolled switches (diodes). Due to elimination of controlled switches, the corresponding auxiliary hardware circuit elements like, driver circuits, power supplies and control signals etc. count are minimised. This improves the system reliability and minimise the cost and weight of converter system. The developmental aspects, operating principle, mathematical formulation and control implementation of proposed topology are discussed in detail. Relative comparison with 3P-3L-MPC-MLT, 3P-2L-MPC-MLT and counterpart iii unidirectional topologies are also presented in this work. In spite of having number of advantages in MLCs, the DC link capacitor’s voltage imbalance is an inherent constraint in MPC-MLCTs. All the proposed topologies presented in this work are MPC-MLCT structured. Therefore, there is a need to take care of DC link capacitors voltage imbalance issue. Currently reported PWM techniques in the literature consider both input line current control and DC bus capacitor voltage balancing simultaneously as well as separately by introducing external balancing circuit (EBC). In present work, author investigated both the methods with respect to current quality, DC voltage regulation and DC link capacitor voltage balancing. Based on above comparison, an appropriate solution is proposed to be adopted in the converter applications. The validation of proposed multilevel converters is carried out at five level operation. 3.3kV grid voltage and 10MW/15MW load variation in MATLAB/ Simulink platform is used to investigate the steady state and transient performance of proposed topologies under the following tested conditions; (i) Rectifier and inversion mode of operation (ii) Balanced supply (iii) Single phase voltage sag condition with 50% degree fo unbalance (iv) Load change (v) DC bus voltage change Negative sequence elimination algorithm with phase disposition pulse width (PDPWM) modulation technique is implemented. During all tested conditions, the shape, harmonic spectrum and balanced nature of input line currents, ripple in regulated dc link voltage, and input power factor are given. To substantiate the viability and effectiveness of various proposed MPC-MLC topologies the following prototypes are designed and developed in the laboratory. 1. Three phase three Leg MPC-5L Topology (3P-3L-MPC-5LT). iv 2. Three phase two Leg MPC-5L Topology (3P-2L-MPC-5LT). 3. Three phase three Leg MPC-5LU Topology (3P-3L-MPC-5LUT). Different hardware auxiliary circuits such as pulse amplification, isolation circuit, dead-band circuit, voltage and current sensor circuits are developed in the laboratory to build the experimental converter types. For these prototypes, grid connected applications are developed. RT-lab real time digital simulator with meta controller software interface and spartan-3 board is used for hardware interface. Negative sequence elimination control algorithm with PD-PWM technique is implemented in the MATLAB/Simulink and compiled by using the meta controller interface to generate the switching signals for the different proposed MPC-MLC topologies. The downscale experimentation is performed on proposed topologies and comparative analysis is given with downscaled MATLAB/Simulation results. The experimental results are found to be in good agreement with the simulation results. The summery of author contribution is given in schematic below,