Please use this identifier to cite or link to this item: http://localhost:8081/jspui/handle/123456789/15006
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dc.contributor.authorMandrik, Srijan-
dc.date.accessioned2021-08-04T05:35:54Z-
dc.date.available2021-08-04T05:35:54Z-
dc.date.issued2013-06-
dc.identifier.urihttp://localhost:8081/xmlui/handle/123456789/15006-
dc.description.abstractDue to its short channel immunity and improved transport property, Silicon Nanowire Field Effect Transistors (SNFETs) is gaining attention as a very good substitute for planar MOSFET devices. In this work effects of Negative Bias Temperature Stability (NBTI) in p type Silicon Nanowire Field Effect Transistor (SNFET) is studied for different values of stress time, stress voltages and operating temperature. After the removal of stress the device recovers to a certain extent. On the fly (OTF) method is implemented to prevent the device from unwanted recovery. This work includes basics of NBTI, different methods of on the fly (OTF) measurement (that is measurement during the application of stress) and the LabVlEW programs for the measurement of NBTI. The degradation in the device parameters such as threshold voltage and linear drain current have been observed and explained. The results show a faster initial degradation compared to planar MOSFETs and a comparatively quicker saturation time .Duc to gate all around structure of SNFET, there is change in behavior of the device to NBTI as compared to planar MOSFETs. We have compared our results with NBTI model in SNFET for 2-D hydrogen diffusion and hole trapping.en_US
dc.description.sponsorshipINDIAN INSTITUTE OF TECHNOLOGY ROORKEEen_US
dc.language.isoen.en_US
dc.publisherI I T ROORKEEen_US
dc.subjectChannel Immunityen_US
dc.subjectImproved Transport Propertyen_US
dc.subjectStress Voltagesen_US
dc.subjectOperating Temperatureen_US
dc.titleSTUDY OF NBTI IN SILICON BASED NANOWIRE FETen_US
dc.typeOtheren_US
dc.accession.numberG22214en_US
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