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|Title:||A LOW POWER SAR ADC DESIGN FOR MEDICAL IMPLANT DEVICES|
|Authors:||Singh, Ajay Kumar|
|Keywords:||Digital Converters;Design;Environment;Cadence Virtuoso|
|Publisher:||I I T ROORKEE|
|Abstract:||The Analog to Digital Converters represent one half of the link between the world we live in - analog - and the digital world of computers, which can handle the computations required in digital signal processing. This dissertation report is focused on ADCs for biomedical applications, where ultra-low power consumption and small form factor is required with medium frequency range. Successive approximation register analog-to-digital converters (SAR ADCs) are attractive when low power operation is important and high-speed operation is not a concern. SAR ADCs appear to be most promising candidate for implantable biosensors, such as implantable heart-rate sensors or sensors used in neuroprosthesis applications. This dissertation report presents a 10-bit successive approximation register ADC design for medical implant devices. Two step capacitor switching is implemented using delay based control logic to reduce DAC power consumption. A dual supply scheme is used to further reduce the power consumption of SAR Logic. SAR logic is operated at 400mV while other analog circuits at lv. Maximum simplicity is provided on the ADC's high voltage level architecture, while all the complicated circuit for charge sharing switching scheme is implemented in lover voltage level along with the digital control logic circuit. Full range sampling is used to minimize the required voltage level. The ADC is designed in GPDK 90nm process and simulated in Cadence Virtuoso Front and Back Design Environment. It consumes 24nW and achieves an ENOB of 9.2 bits.|
|Research Supervisor/ Guide:||Gupta, Sudeb Das|
Saxena, Ashok K.
|Appears in Collections:||MASTERS' THESES (E & C)|
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|G22213.pdf||10.55 MB||Adobe PDF||View/Open|
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