On-Chip Timing Slack Monitors for Low Power Applications

Abstract

With increased use of portable computing devices, the energy e ciency has emerged as one of the most important requirements in VLSI circuits. Escalating process, voltage and temperature (PVT) variations with technology scaling pose critical challenges to meet the performance speci cations of energy and power e cient systems in nanometer technologies. Moreover, aging e ect severely limits the reliability of CMOS devices in nanometer tech- nologies. To encounter such variations, the clock frequency or supply voltage guard bands are provided considering the worst case variations which lead to the performance degrada- tion or increase the power consumption. The supply voltage scaling is one of the e ective ways to reduce the power consumption as the dynamic power is proportional to square of supply voltage. In ultra-low voltage operation, the guard bands are very high as the PVT variations result in large delay variations due to the exponential relation between current and supply voltage. Reducing these guard bands signi cantly increase the performance or reduce energy consumption. The increased probability of timing errors due to large variations is a major challenge in the reduction of timing or supply voltage margins. Critical path replica circuits can be used to reduce timing margins but these circuits can account for global variations which common to a die but not local variations which a ect each transistor in a die di erently. In- situ monitoring techniques which monitor critical path delay locally are suitable alternative to critical path replica circuits as they can reduce margins due to all variations. In these techniques, a modi ed ip- op which can monitor the timing error is placed at the end of each critical path. The common in-situ monitoring approaches to reduce the timing margins are timing error detection, timing error prediction and timing error masking. The error detection i techniques detect the occurrence of timing violations and correct them by using instruction replay mechanism. The error masking techniques use error detection techniques to monitor timing error and mask timing error by using time borrowing and clock stretching. The error detection and error masking techniques can reduce timing margins due to all variation as they operate at point of rst failure. The error prediction techniques monitors delayed data to predict possible occurrence of timing errors and can reduce margins due to slowly changing variations.