ANALYSIS AND MODELLING OF SPACER BASED GATE-ALL-AROUND RECONFIGURABLE DEVICE

Abstract

As the scaling limit is gradually reaching its ultimatum, the devices with multiple functionalities such as TFET, multi gate FiNFET, Silicon nanowire FET are been thoroughly investigated. Silicon nanowire-field-effect transistors (SiNWFETs) are among those devices which can replace the planar as well as fin-shaped field-effect transistors (FinFETs). One of the major drawbacks of the conventional CMOS technology is the inability to reconfigure it. To deal with this problem nanoscale technology with flexible configurability has recently gained a lot of attention in the device research community. An axial silicon nanowire transistor which can be programmed dynamically as n- or p-FET by externally tuning the applied gate voltage forms the modern day reconfigurable field effect transistor (RFET). This device mainly exploits the interesting and unique properties of metal-silicide Schottky junctions to tune the polarity of charge carriers. In a RFET apart from the three electrodes which are common in any field effect transistor, a fourth one acts as an external electric signal to select the desired FET characteristics. This new technology also provides a lot of advantages in terms of fabrication ease using the traditional bottom-up approach. The channel is almost doping free which leads to lesser short channel effects (SCE’s) and the S/D contacts are also metallic which aids its possibility to become a lean technology in upcoming days. Enhanced electrical performance in terms of extremely low gate leakage makes it highly desirable for future low power digital applications. Noteworthy maturity in complex logic and circuit implementation with fewer numbers of transistors than usual has also been recently portrayed using this novel platform. Unlike any other field effect transistor dependent on band to band tunneling (BTBT) for its on-current generation like tunnel field effect transistor (TFET), RFETs too suffer from various challenges and one of them is lower current drive and higher subthreshold swing (S/S) as compared to other planar devices. In view of these drawbacks, modification to the existing RFET architecture leading to a new device concept is necessary. The objective of this thesis is many folds, firstly, to design for the first time a source/drain (S/D) spacer based underlap ambipolar silicon nanowire field-effect transistor device structure which shows enhanced electrical performance over the existing ambipolar topologies. The main reason behind these improvements is the ability of S/D spacers to ii terminate the fringe field lines in to the Schottky contact more nicely which increases the junction electric field and hence the BTBT rate is boosted. The next aim is optimization of various device aspects like spacer material type and length of spacer (Lsp), gate dielectric and its thickness (tox) and inters gate distance (dG1G2) using rigorous coupled 3-D Technology Computer Aided Design (TCAD) numerical device simulations. A systematic investigation of the impact of these critical design parameters on the vital device performance parameters, such as ON current, on to off current ratio, Subthreshold swing (S/S), threshold voltage, and transconductance generation factor was done. It was observed that higher spacer lengths, gate and spacer dielectric constants improves the device performance mainly because of better electrostatic coupling between metal gates and Schottky junctions and also due to increase in density of fringe field lines near the metal/semiconductor interface. To acquire a deeper understanding of various physical details behind spacer based performance enhancements over the conventional non-underlap RFET architecture through device level optimizations, the impact of variation in the gate channel underlap (LGCU) and spacer channel underlap region (LSCU) on the device behaviour was also studied. The main aim of shifting to a high-κ gate dielectric is to lower the equivalent oxide thickness (EOT) without making a trade off with the gate leakage. So, the role of gate oxide EOT and scaling properties of the proposed device was also investigated. Since the subthreshold drain current of a RFET depends upon thermionic emission which is itself a temperature dependent phenomenon, the work was further extended to study the temperature dependence of the digital/analog parameters and RF figure of merits of the spacer based RFET and compare the same with the existing RFET topology and other devices which depend on band to band tunneling (BTBT) for their on current generation. Having a better thermal stability over TFET and sufficiently lesser Vth roll-off, the proposed device portrays orders of magnitude reduction in parasitic gate capacitances and intrinsic delay as compared to gate-all-around (GAA) and heterogeneous gate dielectric gate all around (HD GAA) TFET devices over the considered range of temperature, thus ensuring higher switching speed for digital applications. It is found to have a comparatively better analog performance than SiGe and full silicon TFETs with increased values of gm, gm/Id and Av in the considered range of temperature mainly because of BTBT dependent drive current and superior gate control over the silicon channel. Temperature variation of various iii important RF parameters like higher order transconductance coefficients, cut-off frequency (fT), gain bandwidth product (GBW), transit time (τt), device figures of merits (FOMs) VIP2, the third-order intercept point (IIP3) and the third-order intermodulation distortion (IMD3) was shown and the results were also compared with conventional RFET, Si abrupt TFET and SiGe TFET. For most of these metrics, the proposed device shows superior RF performance as compared to its counterparts. The device FOMs were also found to be less sensitive to temperature variations making it more suitable for applications where temperature fluctuation is a major concern. Finally, a physics based compact model was developed for surface potential and drain current for a dual gate (DG) source/drain (S/D) spacer based silicon nanowire reconfigurable field effect transistor. The models were derived by dividing the active portion of the device into several regions based on positioning of the gates, spacers and the metal-silicide Schottky junctions. A charge density expression was first developed and the 2-D Poisson’s equation was self consistently solved for various sub-regions of the device. By using the charge density expression, a single-piece-approximation of the long channel surface potential was developed. Then it was added to the potential distribution at the Schottky junctions which is then solved by using a quasi-2D approach. The drain current was modeled by first finding the barrier height required for the carriers to overcome the maximum potential barrier induced in the silicon channel by the control gate near the source end of the device which was then used to find out the current through the Schottky barriers. This was equated based on the principle of current continuity with the drift diffusion current in the channel obtained by using the earlier derived charged density expression to generate a final drain current expression. The accuracy of the derived results was tested using 3-D numerical TCAD simulations. This work was lastly concluded by developing a Verilog-A model of the device under consideration for investigating the spacer induced performance improvements over the conventional non-underlap RFET with respect to delay reduction mainly in logic applications.