MODELING OF MULTIGATE MULTIFIN FINFET FOR HIGH FREQUENCY APPLICATIONS

Abstract

Many efforts have been concentrated on the merging of communication and computation technologies which requires low power, high-frequency techniques which results in a trade-off between power consumption and system performance. In the past decade, horizontal field effect devices (MESFETs and HEMTs) and vertical bipolar device (HBT) reigned the high-frequency applications industry. The applications where input noise and total power are the major issues, FETs are preferable and where matching, frequency variation, high flicker noise are a concern, HBTs are leading technology. However, it has limited applicability in high-density low power circuit applications. The high volume integration and acceptable performance capability of Multigate FET have given the semiconductor industry a boost. In the last few decades due to aggressive scaling, there has been a large change in the device physics. Challenges of continuous scaling and enhanced speed are overcome by using various geometrical shape of the gate, increased number of channel controlling surfaces, Source/Drain (S/D) Engineering, Gate engineering, amongst others. FinFET technology comes forth as a major milestone in the field of nano-electronics after successfully launching the tri-gate transistors commercially in the 22 nm technology node due to its excellent performance. It has taken its rightful place amongst semiconductor industries/foundries. Nonetheless, possessing the same challenges faced by any budding technology, FinFET with sub-20 nm feature size also confronted several design/fabrication challenges. The technological confinement is the main reason behind the deterioration of the short-channel characteristics. To overcome these challenges, non-planar undoped channel, graded doping profile of source/drain, crystal orientation, selectively deposited raised source/drain engineering are incorporated. In past decade, industry demand was to have a mix of mixed-mode, analog/RF and digital applications with FinFETs. This necessitates improvement of the FinFET high-frequency performance and extraction of microwave models since accurate and complete high-frequency transistor modeling plays a key i role. FinFETs present good scalability, less leakage and intra-die variability as well as suppression of short channel effects. The serious shortcomings of future device miniaturization are that the scaling of parasitic components is not in proportion to area. For short channel, the ratio of intrinsic and extrinsic capacitance drastically degraded which means total gate capacitance is controlled by the extrinsic part. Therefore, the key factors which often contribute to worsening the RF performance are the higher magnitude of parasitics of quasi-planar structure and fin width quantization of FinFETs. Another important factor which regulates the fundamental limits to signal resolution is total noise which is dominated by thermal noise component at radio frequency (RF). The limitations are imposed due to an exorbitant increase in parasitics and noise (sources are additional fringing field emanating from finite gate electrode thickness of FinFET) that in turn worsens the dynamic performance. Therefore, the RF circuit designers need to adapt their designs taking into account these critical issues so as to improve overall performance in terms of device/circuit parameters such as unity gain cut-off frequency ( fT ) and maximum frequency of operation ( fmax), minimum noise figure (NFmin) and output power (Pout ) for RF noise and power application. In this thesis, we proposed an analytical model based on successive conformal mapping to compute the bias dependent inner fringe capacitance in nonplanar multigate MOSFET structure with doping modulated source/drain (S/D) and gate underlap for sub-20 nm node. The conventional analytical model of capacitance and resistance for planar MOSFET cannot be applied to the nonplanar multigate FinFET. This model considers 3-D devices fabricated on bulk oxide, gate-S/D extension with non-uniform doping gradient and spacers. The percentage variation of inner fringe capacitance with respect to underlap length is studied for various fin width and oxide thickness. From this proposed model, we efficiently give physical insight of the contribution of various portion of the MOSFET nonplanar structure quantitatively. Hence, the results obtained can provide device design guidelines for reducing fringe capacitance and hence an improved speed. We also describe in this proposed analytical model of outer fringe capacitances of a 3D architecture of multi-fin device under study. The models are based on different assumptions and ii fitting parameters, the agreement among results are found quite good thereby verifying the validity of the model. This distinctness has been carefully explored by analyzing the individual modeling parameters and the physical phenomenon contributing to gate parasitic capacitances. The development of parasitic model facilitate accurate quantitative prediction of the parasitics introduced by each part of the device structure. We also leveraged the thermal noise model to evaluate accurate noise performance at the circuit level. The proposed analytical model is used to evaluate the inversion charge, electric field, gate resistance, source drain resistance and consequently, additional noise caused by the three-dimensional structure of FinFET. It is observed that additional fringe field increases its minimum noise figure (NFmin) and noise resistance (Rn) by approximately 1dB and 100W respectively and optimum admittance increases to 5.45 m0 at 20 GHz for a device operating under saturation region. Motivated by the excellent device electrostatics, we further explore the possibility of a generalised model and proposed a new hybridized fuzzy-neural predictive intelligent (HFNPI) model for predicting FinFET model based on biased and structural parameters. It assesses the performance of resultant structure on the basis of selected RF figure-of-merit (RF-FOM). Based on the application requirements, RF figure-of-merit such as fT and fmax are used as appropriate performance criteria to analyze the device performance. The combination of fuzzy and Artificial Neural Network (ANN) system have been used to model fuzzy multi-criteria decision process. Each parameter has its own impact (positive/negative) on the figure-of-merit (FOM). It is certainly complex to select the best factors specifically when the data set is incomplete or imprecise. The framework for the HFNPI model has underlapped FinFET structural/process parameters. The model was evaluated on the basis of TCAD simulator data set for determining the dependence of fT and fmax (at fixed bias condition of VGS and VDS) on geometrical/process parameters gate length (Lg), underlap length (Lun), fin thickness (Tf in), fin height (Hf in), spacer thickness (Lsp), channel doping (Nch) etc. The best suitable model parameters are then selected based on the most dominating combination of input criteria for augmenting the RF design metrics. It is observed that the performance parameter fT and fmax can be accurately reproduced by the resulting model, is determined by the non-linear mapping performed by the fuzzy membership functions. The developed algorithm exploit the iii feature of both fuzzy and neural network which results in a reduction of computation time and the exact variation of more than three parameters can be analyzed for best optimization structure. It is able to find out the most dominating parameters to be tuned. The HFNPI model can be used in a CAD and optimization providing a faster solution and speed up design cycle by reducing the time for geometrical dimensions determination for the required application.