VARIATION AWARE MEMORY DESIGN FOR LOW POWER APPLICATIONS

Abstract

Semiconductor industry has enjoyed the incredible benefits of the scaling trends over the last few decades. These benefits include high performance, high density on smaller chip so as to have a lesser overall cost. However, from the last few years, technology scaling has prompted the interest for low power designs to grow extensively. Due to the benefits of having information in hand, the battery operated portable devices like laptops, mobile phones, PDA (personal digital assistants) etc have become popular and these devices are now an essential need of everyone. To satisfy this requirement, power-aware design has become the preferred choice of every designer. Moreover, to meet the requirement of these high performance digital systems, a large portion of the chip area is devoted to embedded Static Random Access Memories (SRAMs). The numbers of cache SRAMs are increasing in the modern processors to enhance the performance of the system. Because of the large portion being occupied by on-chip SRAM in a system, the overall performance including power and cost of the system rely on the performance of SRAM. Thus, the system power-efficiency, reliability, performance and overall costs can be significantly improved by reducing the power dissipation in high performance reliable SRAMs. But, SRAM faces several challenges to achieve low power operation. In order to have the power density within limits as is essential by the poweraware applications, the power supply is scaled with technology scaling. Unfortunately, this scaling of power supply is not enough to have the desired goal of low power. Further, the performance in terms of speed is reducing with voltage scaling. To meet this performance criterion, threshold voltage (VTH) scaling is used. However, sub-threshold leakage current increases exponentially with threshold voltage scaling which causes an increase in the static power consumption. Consequently, the static power consumption of CMOS SRAM become an important challenge in modern era due to technology evolutions. Sub-threshold leakage is an obstacle for low power system, as it contributes a major portion of the total power consumption in low dimensional system. In addition to the sub-threshold leakage current, short channel effects also becomes prominent with the continuous device and ii voltage scaling. The random microscopic fluctuations in number and position of dopant atoms in the channel region of MOSFET causes the variations in the essential device parameters like threshold voltage, sub-threshold swing, drain current and subthreshold leakage current etc. This causes variation in electrical properties of the device resulting in an unpredictable device behaviour. As an outcome, the variation in the performance metrics of the circuit become challenging to deal. Thus, this intrinsic variation effect poses a barrier to further reduction in the supply voltage and channel length and hence in the minimization of the power. Another challenge caused by the miniaturization is the reliability issues due to radiation effects. The quest for high performance and high density systems led the use of advanced fabrication techniques (like reactive ion etching, electron beam lithography, X-Ray lithography etc.) and can cause major radiation damage. The radiation damages causes unstability in the circuit operation or sometimes complete failure of the device. These radiation damages are more prominent in the circuits having storage properties like flip flop, SRAMs etc. The reliability of the SRAM gets affected due to these radiation effects. So, the designing of low power SRAM requires a balance between performance, area and power consumption. The main objectives of the thesis are to scrutinize the impact of process variations on the stability and reliability of the SRAM and to design a variation aware low power SRAM. The read/write stability analysis of 6T SRAM cell is performed at worst process corners. Data retention voltage (DRV) of 6T SRAM cell is analysed and the modified analytical model for DRV of 6T SRAM cell is proposed. The process corner analysis with temperature variations, for DRV of 6T, 8T and 10T SRAM cell, is performed to find the minimum voltage for the standby operation of SRAM cell. Monte-Carlo simulations are carried out to prove the accuracy of the DRV model. The semi-analytical model for the Write Static Noise Margin (WSNM) is proposed for the write stability of the 6T SRAM cell for the first time. Extensive simulations for 6T, 8T and 10T SRAM cells are carried out at different process corners, at different technology nodes for the accuracy of WSNM model. In addition to the process variability analysis of SRAM, variation aware low power SRAM is proposed through this work. Low power variation tolerant 9T SRAM cell is proposed. Simulations are performed for the hold, read/write stability of the proposed cell under process variations. Monte Carlo simulations under iii variations are performed to prove robustness of the cell. 9T SRAM cell is compared with 6T, 8T and 10T SRAM cells through simulations for the reliability, stability and overall performance of the 9T SRAM cell. The proposed cell is found to be not only process variation invariant, but it also has radiation hardening properties also. For proper functionality of low power SRAM, radiation effects on the SRAM cell are examined. Radiation hardened circuit is proposed for the radiation hardness of the SRAM cell. Radiation hardened (RH) circuit is capable of detecting and self correcting single fault if occur due to radiation effect. Besides this, the limitation of the circuit is that it can detect and correct error only due single event upset at one node. Though, this RH circuit can be applied to any SRAM having word-line to activate the write operation and bit-line having the data to be written on the SRAM cell, but it gives appropriate reliability properties with the proposed 9T SRAM cell. The analysis of this RH circuit is performed with 9T and 6T SRAM cell.