MODELING AND SIMULATION OF DOUBLE GATE TUNNEL FIELD EFFECT TRANSISTOR (DG-TFET)

Abstract

As the devi e sizes are shrinking for onventional metal-oxide-semi ondu tor (MOS) FET, the short hannel e e ts su h as sub-threshold urrent, DIBL et . are dominating. Also, the devi e sub-threshold slope in reases exponentially with the temperature. So, there is a need to nd a solution to these issues. The possible solutions for these problems led to the investigation of new devi es: Multigate MOSFET, Nanowires, nano-ele trome hani al FET, impa t ionization-FET, Tunnel FETs, et . Among all these devi es, the TFETs have ome out to be the most promising su essors of (MOS) FETs due to their abil- ity for temperature independent sub-60mV/de sub-threshold swing, very low o urrent (~femtoamperes), and better s alability to de a-nanometers gate length. Su h a redu ed swing is a ne essary requirement for the ultra-low power, ultra-low voltage operation for the next generation of transistors. It an be on luded that the TFET is still the most promising devi e both due to its strong similarity with the MOSFET on guration, whi h allows signi ant re-use of the MOSFET expertise and its enhan ed output hara teris- ti s are almost temperature independent, thus, TFETs are better andidates for higher temperature appli ations. Introdu tion of TFETs is presented in Chapter 1. This hapter in ludes the motivation for resear h in the area of TFETs, working prin iples, followed by a omparison with onvention MOSFET. Next the te hni al gaps are identi ed and then the problem is de ned for this resear h work. The last subse tion of this hapter gives the outline of the thesis. An extensive literature survey is done in Chapter 2, whi h in ludes di erent aspe ts of TFET like: fabri ation, drain urrent boost up te hnologies, hanges in hara teristi s due to III-V materials, TFET as high temperature appli ations and there e e ts. Survey on TFETs appli ations is also done in this work. Although, the whole work is arried out using 2D sili on Double Gate (DG) TFETs with sharp doping pro les at the sour e and drain edges. First, the fo us is to elaborate the fa t that the hannel inversion phenomenon in TFET is not related to the threshold voltage. This phenomenon is studied with extensive TCAD simulations, and it has been found that the hannel inversion might or might not o ur at the threshold voltage, and the hannel inversion depends on the applied drain voltage. This work serves as rst part of Chapter 3, and is basis for analyti al model presented for sub-threshold region in Chapter 4. Next, the fo us is on drain extension region resistive e e ts. The drain extension resistive e e ts on TFET devi e are evaluated using TCAD simulations. To ompare the extension region e e ts, the top and bottom sides of sour e/drain are tied together that will make i the extension region resistan e zero. Now, the mid hannel ele tri al parameters like surfa e, and mid hannel potential, quasi fermi potential et . are studied and dis ussed with, and without the sour e/drain extension regions. It is found that there is a ountable potential drop in the hannel when the sour e/drain resistan e is taken into onsideration. This work serves as se ond part of Chapter 3, and is basis for the semi-analyti al model presented in Chapter 5. Next, the fo us has been on the development of analyti al modeling in the hannel region, in Chapter 4. This modeling is a omplished in two parts: a) the sub-threshold region potential and ele tri eld are modeled by solving the 2D Poisson's equation with ap- propriate boundary onditions, b) the post-threshold modeling is performed using semi- analyti al approa h. The modeling results are veri ed, and validated with the results obtained from TCAD devi e simulations. The model is having exibility like indepen- dent gate terminals, and gate oxide, asymmetry in gates, and gate work-fun tions, gate length variability et . The sub-threshold model is valid for all regions where Vgs < Vds. In Chapter 5, we develop the semi analyti al model for strong inversion region, this is referred as the post-threshold region in this work. Post-threshold region is de ned as the region where Vgs ≥ Vds, in this region if we apply pure analyti al modeling then we have to in lude the 1-D S hrodinger's equation to in lude the quantum e e ts. For this model we have used 1-D Poisson's equation a ross the mid hannel and its solution is veri ed with the TCAD data. The tting parameter extra ted is studied and ompared with the simulated data with varying di erent devi e physi al parameters like: gate length, n width et . Further, the drain extension region width e e ts are studied in the I-V hara teristi s of TFETs, and the same are applied for ring os illator simulations in Chapter 6. It is seen that the hange in the drain extension region width has a great impa t on the devi e delay, and operating frequen y. The results are dis ussed using the resistive, and apa itive e e ts of the devi e. The results are ompared for delay, and the jitter with variations in the power supply and the sili on width of the extension region. It is found that the in rease in drain extension region length, will in rease the propagation delay of RO that in turn makes the devi e faster while the peak overshoot, and undershoot also in reases. Thus, a trade o must be maintained in order to get best results in terms of speed, and swit hing power dissipation. The thesis work is on luded with summary of the work done and also the further s ope of resear h are enumerated