TIMING MODELS FOR EFFICIENT CHARACTERIZATION OF NANOSCALE VLSI SINGLE STAGE STANDARD CELLS

Abstract

In nanometer range VLSI te hnologies, semi- ustom hip design approa h using pre- designed and pre- hara terized standard ells is popular be ause of in reasing omplexity. For e ient ir uit design, these standard ells are pre- hara terized for delay, transition times, terminal apa itan es, power dissipation, noise and area using SPICE simulations. The traditional Non Linear Delay Models (NLDM) based Lookup Table (LUT) approa h for standard ell hara terization and Stati Timing Analysis (STA) is fa ing serious hal- lenges in nanometer te hnologies, be ause it does not a ount for the nature of input and output terminal voltage transitions. Be ause of voltage dependent values of e e tive a- pa itan es of devi e and inter onne ts, it be omes important to onsider the nature of output transition. To over ome these limitations, resear hers introdu ed Current Sour e Modeling (CSM), in whi h for a given value of load apa itan e, the value of output volt- age and equivalent ir uit parameters of the standard ell are given as a fun tion of input voltage. This in reases the omplexity of the model and the amount of data to be stored for standard ell hara terization. To solve these issues, vendors found the models as a middle path (between NLDM and CSM), known as vendor CSM formats. These vendor CSM formats are E e tive CSM (ECSM) and Composite CSM (CCSM) . For a given input transition time (TR) and load apa itan e (Cl=Ceff ) values, ECSM stores the times at whi h the output voltage waveform rosses ertain prede ned threshold points, whereas CCSM stores the output urrent values at spe i ed voltage level points. Both the vendor models are equivalent and one an be derived from the other. Vendor CSMs use Lookup Table (LUT) based format for representing hara terization data. The major issue with ECSM hara terization is that it requires re- hara terization of standard ells with variation in ell size, layout dependent parameters, temperature, supply voltage and devi e model updates. This re- hara terization is highly time onsuming. Therefore, there is a need for a model whi h is more e ient in standard ell hara terization, thus saving time and e ort. In this thesis, we undertake a detailed study of existing timing/delay models of CMOS inverter and NAND gate standard ells. We nd that these delay models are unsuitable for use in standard ell hara terization, be ause the region of validity in TR , Cl spa e is not lear. Apart from this ell size, layout dependent parameters, power supply voltage and temperature variations are also not inputs to su h models. In addition, it is seen that the intermediate node voltage transition of the series sta k nMOS devi es of a NAND gate, whi h plays an important role in sub-nanometer te hnology nodes, has not been onsidered appropriately in earlier models. We show that onsidering these issues in standard ell hara terization, the re- hara terization e ort would in rease signi antly. For an e ient ECSM hara terization, we developed the timing models for CMOS inverter and 2-input NAND gate (therefore, for 2-input NOR gate also), to redu e the re- hara terization e ort. All the multistage ombinational ells an be derived from these basi ells. Firstly, we propose the analyti al timing models relating all the Threshold i Crossing Points (TCPs) of output transition with TR, Cl values, for CMOS inverter and 2-input NAND gate. We then identify the region of validity of the model in TR, Cl spa e used in hara terization LUTs. It makes the timing models useable in redu ing the HSPICE simulations in ECSM library hara terization. Further, we identify the relationships of model oe ients with ell size, pro ess indu ed me hani al stress, temperature and supply voltage variation. Our NAND gate timing models are robust be ause of an appropriate and detailed onsideration of voltage transition at the intermediate node of the series sta k of nMOS devi es. For this, we onsider the input to intermediate node apa itive oupling e e t, parasiti apa itan es at the intermediate node and the regions of operation of the two nMOS devi es pla ed in series sta k. We present the timing models for 2-input NAND gate, onsidering the following two ases : 1) When upper nMOS transistor in the series sta k swit hes; and 2) When lower nMOS transistor in the series sta k swit hes. In this thesis, we show that the use of these models in standard ell hara terization redu es the number of SPICE simulations by 50% and 67% for CMOS inverter and 2-input NAND gate, respe tively. We also show that our timing models remain valid with PVT variations. This would help in redu ing the re- hara terization e ort signi antly (nearly 85% redu tion in SPICE simulations) for standard ell libraries. Further, we present an analyti al overshoot timing model for CMOS inverter and NAND gate for a urate timing analysis. For NAND gate overshoot modeling, we see that an in lusion of intermediate node voltage transition with appropriate assumptions lead to a urate estimation (max. error is 2.5% with respe t to HSPICE simulations) of overshoot timing values for Case 1 and 2, respe tively.