DUAL-k SPACER ENGINEERED DEVICES FOR HIGH PERFORMANCE DIGITAL CIRCUIT/SRAM APPLICATIONS

Abstract

FinFET technology has emerged as a major milestone in the field of nano-electronics after the announcement by leading semiconductor industry to use the tri-gate transistors commercially in the 22 nm technology node. In order to keep pace with Intel and TSMC, 10 nm and 14 nm FinFET process nodes are rapidly emerging as preferred choice amongst other semiconductor industries/foundries in near future. However, similar to the problems faced by any new technology, FinFET with sub-20 nm feature size also faces several design challenges. Most of these challenges arise due to technological restriction that can deteriorate the short channel characteristics. This necessitates the use of undoped underlap regions that otherwise increases the channel resistance and reduces the drive current. In the past decade, high permittivity (k) spacer materials act as key enabler in enhancing the device performance that provides strong field coupling between the gate and the undoped underlap region and hence reduces the raised source/drain series resistance. However, it has limited applicability in high-performance circuit/SRAM applications. The limitations are imposed due to exorbitant increase in fringe capacitance that in turn worsens the dynamic performance. The other two inherent challenges associated with FinFET are higher magnitude of parasitic (due to its 3D nature) and fin width quantization. Therefore, the digital circuit designers need to adapt their designs taking into account these critical issues so as to improve overall performance in terms of device/circuit parameters such as ION, IOFF, noise-immunity, and the switching speed etc. Process variability has emerged as one of the major concern in sub-20 nm gate lengths. The random variability in device increases sharply with reduced feature size that can fail out any design both in digital as well as analog domain. Therefore, it is necessary to thoroughly investigate novel device architectures with their circuit/SRAM suitability and tolerance to random statistical variations. In this thesis, we primarily focus towards the novel device architecture abbreviated as dual-k spacer FinFET that intelligently uses the high permittivity spacer targeting for high-performance device-circuit co-design and its immunity to random statistical and structural variations. The dual-permittivity spacer concept and the optimization strategy are presented for the tri-gate FinFET device under study. We ii also describe the proposed symmetric and asymmetric dual-k architectures, their fabrication methodology and superior ON- and OFF-state electrostatics over the conventional (single/low-k spacer) as well as the purely high-k spacer underlap FinFET structure. It is observed that the carrier concentration increases with an increase in the inner high-k spacer length (Lhk) till it reaches an optimum value. Beyond this optimum point, the fringing-field lines do not affect much the laterally diffused S/D region that already has very high carrier concentration. Therefore, there is no need to place high-k spacers above the highly doped laterally diffused area that may otherwise lead to higher parasitic capacitances. Consequently, beyond an optimal Lhk, the device performance starts degrading. The difference in spacer permittivity at high-k/low-k interface region changes the electric field path that results in better electrostatics in both ON and OFF-state. We also physically interpret the ON/OFF state electrostatics associated with dual-k structure with an increase in inner spacer k value. From this, an important observation is made that the conduction band energy barrier (in ON-state) directly under the gate is significantly affected in proposed dual-k architectures which otherwise remains same in purely high-k device even though the inner spacer permittivity is increased substantially. In addition, a detailed TCAD comparative analysis between symmetric and asymmetric architectures is demonstrated that clearly presents the competing effects of high permittivity spaces on device electrostatics. It is observed from the obtained results that the source side spacer mainly governs the charge transport from source to drain, however, the drain side spacer helps to enhance the current magnitude. We also comprehensively study the role of fringe capacitances associated with proposed dual-k architectures that demonstrates the suitability of high-k spacer materials for improving noise-margin and delay performances, simultaneously. Although, the dual-k structures also exhibits larger fringe capacitances in comparison to conventional FinFET, but with an optimized inner spacer length, the proposed SymD-k and AsymD-kS architectures shows better inverter/RO3 delay performances. This superior delay performance is due to the increased gate-to-source capacitance component. On the other hand, the inverter delay worsens in AsymD-kD device because of the high value of Miller capacitance. For AsymD-kS and SymD-k architectures, it is observed that the gate-to-source capacitance increases sharply up to an optimum point and thereafter decreases marginally. However, for AsymD-kD iii architecture, it remains low and almost constant. Moreover, an important and novel observation is made that the delay performance improvement is more pronounced with higher permittivity of the spacers in dual-k spacer technology that otherwise worsen in case of purely high-k architectures. Motivated by the superior device/circuit electrostatics, we further explore the possibility of proposed symmetric and asymmetric dual-k architectures for augmenting the SRAM design metrics such as SNM, read/write access time, and the total leakage power. Furthermore, we investigate the tolerance of symmetric and asymmetric dual-k spacer architectures and its SRAM performance by random statistical and structural parametric variations. In addition to the superior device electrostatics and better static/dynamic circuit performance, it is observed that both the symmetric and asymmetric dual-k tri-gate FinFET structures also exhibits better device and circuit immunity to random variations and lesser sensitivity to key structural parameters in comparison to the conventional FinFET based circuits