MODELING OF CROSSTALK EFFECTS IN CMOS GATE DRIVEN ON-CHIP INTERCONNECTS USING FDTD TECHNIQUE

Abstract

Advancement in very large scale integration (VLSI) technology offers gigascale integrated circuits in a system on-chip. In these circuits, interconnects play a key role in determining circuit performance, such as time delay and power consumption. At high operating frequencies, the closely packed interconnects produce transient crosstalk. The crosstalk noise strongly influences the signal propagation delay and causes the logic or functional failure. Over the years, several mathematical models have been proposed for the analysis of CMOS gate driven coupled on-chip interconnects. However, most of these crosstalk noise models approximately considered the non-linear CMOS driver as a linear resistor. This approximation is not valid for on-chip interconnects because during the input and output transition states the transistor operates in cutoff, linear and saturation regions. The transistor operating time in the saturation region is about 50% during the transition period. Thus, assuming that the transistor operates in the linear region leads to severe errors in the performance estimation of the driver-interconnectload system. Therefore, it is necessary to develop an accurate model that appropriately considers the non-linear effects of CMOS driver and accurately measures the crosstalk induced performance parameters of on-chip interconnects. This thesis presents an accurate and time efficient model of CMOS gate driven coupled on-chip interconnects for crosstalk induced performance analysis. The proposed model successfully incorporates the non-linear effects of CMOS driver. The model is developed using the finite-difference time-domain (FDTD) technique for coupled on-chip interconnects, whereas, the CMOS driver is modeled by either n-th power law or modified alpha power law model. The model is validated by comparing the results with HSPICE simulations. It is observed that the results of the proposed model closely matches with that of HSPICE simulations. Encouragingly, the FDTD model is highly time efficient than the HSPICE. The conventional copper interconnect suffers from low reliability with down scaling of interconnect dimensions. The reliability of Cu reduces due to the electromigration induced problems such as hillock and void formations. Moreover, with highly scaled dimensions the resistivity of Cu increases due to electron-surface ii scattering and grain-boundary scattering. Therefore, researchers are forced to find an alternative material for on-chip interconnects. Carbon nanotubes (CNTs) have been proposed as a promising interconnect material. A portion of this thesis is focused towards the modeling of multi-walled CNT (MWCNT) interconnects. An accurate FDTD model is presented while incorporating the quantum effects of nanowire and non-linear effects of CMOS driver. To reduce the computational effort required for analyzing the CMOS driver, a simplified but accurate model is employed, named as, modified alpha power law model. The crosstalk noise is comprehensively analyzed by examining both functional and dynamic crosstalk effects. Graphene nanoribbon (GNR), a strip of ultra-thin width graphene layer, has also been considered aggressively by the researchers as a potential alternative material for realizing on-chip interconnects. Most of the physical and electrical properties of GNRs are similar to that of CNTs; however, the major advantage of GNRs over CNTs is that both transistor and interconnect can be fabricated on the same graphene layer, thus avoiding the metal-graphene contact problems. This thesis presents an accurate model for the analysis of multi-layer GNR (MLGNR) interconnects. In a more realistic manner, the model incorporates the width dependent mean free path that helps in accurately estimating the crosstalk induced performance in comparison to the conventional models. The stability of the FDTD technique is constrained by the Courant-Friedrichs- Lewy (CFL) stability condition. Hence, beyond the CFL condition, the FDTD technique is unstable and within it, the technique is inefficient. The efficiency improvements in FDTD technique can be addressed, if the CFL stability condition is removed. To improve the efficiency of FDTD technique, an unconditionally stable FDTD (US-FDTD) technique is presented for the analysis of on-chip interconnects. It is observed that the stability of the proposed model is not constrained by the CFL condition and is therefore unconditionally stable. The accuracy of the proposed model is validated against the conventional FDTD model. It is observed that the US-FDTD model is highly time efficient while being as accurate as the conventional FDTD. Moreover, a comparative analysis of crosstalk induced performance is presented among Cu, MWCNT and MLGNR interconnects. It is observed that the MLGNR and MWCNT interconnects outperform the Cu interconnect.