Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/14515
Title: PERFORMANCE ANALYSIS OF GRAPHENE BASED INTERCONNECTS AND THROUGH SILICON VIAS
Authors: Majumder, Manoj Kumar
Keywords: Advancement in VLSI Technology;High-Speed Complex;Increasing Clock Frequency;Interconnect Play
Issue Date: Dec-2014
Publisher: Dept. of Electronics Engineering iit Roorkee
Abstract: Advancement in VLSI technology has lead to the development of high-speed complex integrated circuits (ICs) in deep submicron and nanoscale regime. Due to shrinking feature size and increasing clock frequency, interconnect play an important role in determining the overall chip performance. In current research scenario, interconnect delay dominates over the gate delay. At global level of interconnects, most of the conventional materials (such as Al or Cu) are susceptible to electromigration due to high current density. To avoid such problems, researchers have investigated carbon nanotube (CNT) and graphene nanoribbon (GNR) as prospective interconnect materials in current nano and deep sub-micron technologies. During last decade, a gradual and significant progress in CNT and GNR based interconnects and through silicon vias (TSVs) has provided an alternative design platform to conventional Al and Cu interconnects and vias. A large number of studies have demonstrated different equivalent electrical models of single- and multi-walled CNTs (SWCNTs and MWCNTs) by incorporating unique physical and electron transport properties. However, several challenges related to the structure and modeling of CNT interconnects are yet to be resolved. From fabrication point of view, it is not trivial to control the growth of SWCNTs and MWCNTs with similar diameters in a densely packed bundle. Therefore, researchers have advocated for mixed CNT bundle (MCB) in comparison to purely SWCNT or MWCNT bundles. The crosstalk of a coupled MCB based interconnects and TSV can be substantially reduced by manoeuvring the placement of MWCNTs and SWCNTs in the bundle. Several researchers have reported that the outermost shell of a MWCNT carries lesser current in comparison to the SWCNT with similar diameter. Taking cognizance of these facts, this work analyzes the performance of SWCNT, MWCNT and different configurations of MCB based interconnects and TSVs using comprehensive and accurate analytical models. Depending on the arrangements of SWCNTs and MWCNTs in a bundle, an equivalent RLC model is proposed for SWCNT bundle , MWCNT bundle and mixed CNT bundled interconnects and TSVs. A capacitively coupled three line bus architecture is used to analyze the crosstalk induced delay. For same crosstalk induced delay, the equivalent number of SWCNTs in bundle is obtained for fixed number of shells in MWCNT at global ii interconnect lengths ranging from 100μm to 1000μm. It is observed that same crosstalk induced delay is obtained for fewer numbers of shells using MWCNTs as compared to the number of SWCNTs in a bundle. Further, area comparisons between SWCNT and MWCNT bundles are also made. Moreover, a comprehensive and accurate analytical model of MCB based TSV is introduced, taking into account the MOS effect generated by the presence of TSVs in silicon substrate. The MCB parasitics are accurately modelled by considering diameter dependent mean free path and conducting channels. Using capacitively coupled TSV lines, propagation delay and crosstalk induced delay are analyzed for different topologies of MCB based TSVs wherein MWCNTs are placed at periphery to the centrally located SWCNTs. It is observed that the propagation delay and crosstalk induced delay are significantly reduced for more number of MWCNTs at peripheral layers. In recent years, multi-layered GNR (MLGNR) and multi-walled CNT have rapidly gained importance as emerging materials for realizing on-chip interconnects. However, from the fabrication point of view, MLGNR is preferred over MWCNT due to its better controllability. Therefore, it is important to analyze the performance of MLGNR and MWCNT based on-chip interconnects. The work in this thesis analyzes and compares the propagation delay, bandwidth and relative stability of MLGNR and MWCNT based driver-interconnect-load system for local, semi-global and global lengths. An analytical expression is presented for output voltage waveform and delay. At different interconnect lengths; the number of shells in MWCNT is obtained for a delay performance that is equivalent to a fixed numbers of layers in MLGNR. Further, the area comparisons between MLGNR and MWCNT interconnect are also made. Additionally, a distributed transfer function of higher order is derived and used to obtain the bandwidth and Nyquist stability at local, semi-global and global interconnect lengths. The transfer function accurately takes into account the driver resistive-capacitive parasitics and the imperfect metal-MLGNR/MWCNT contact resistance. It is observed that MLGNR demonstrates a higher bandwidth in comparison to the MWCNT for various interconnect dimensions. However, the Nyquist stability criterion demonstrates that MWCNT is relatively more stable than MLGNR at local interconnect lengths, whereas at semi-global and global interconnect lengths, both the MLGNR and MWCNT are stable.
URI: http://hdl.handle.net/123456789/14515
Research Supervisor/ Guide: Kaushik, B. K.
Manhas, S. k.
metadata.dc.type: Thesis
Appears in Collections:Department of Hydro and Renewable Energy

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