SIMULATION AND MODELLING OF MULTIGATE MOSFETS FOR ANALOG APPLICATIONS

Abstract

Complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) have seen overwhelming growth in electronic industry with gadgets for entertainment, communication, computing, signal processing and other applications. Low power consumption, reduced area, increased speed and lower production cost per chip etc., are some advantages of CMOS technology that have opened the door for integration of millions of transistors on a single chip. It is also believed that, with technology scaling, the trend of rapid improvements in performance of CMOS ICs will continue in near future. Advancement in CMOS technology in modern times has further ensured not only higher packing density but also improved performance in digital, analog and mixed signal circuit design. However, as the number of transistors that are integrated per chip is increased, the problems of leakage currents, thermal management, reliability etc. have also been pronounced. These problems are posing great threat to circuit designer in recent years, because of increasing use of battery operated portable electronic gadgets in various spectrum of life. Starting from micro environmental sensors and radio frequency identification to personal digital assistants like laptops, cell phones, cameras etc., the demand for ultra low power consumption and prolonged battery life is increasing day by day. Therefore, single gate bulk CMOS devices scaled below 100nm gate length are practically losing its credibility with pronounced increase in short channel effects (SCEs) that degrades the battery run time in these portable devices. Multi-gate (MG) MOSFETs such as double gate (DG), triple gate (TG) and gate all around (GAA) MOSFETs etc., on the other hand, posses good properties like, near ideal subthreshold slope, improved threshold voltage roll-off and drain induced barrier lowering (DIBL). ii More importantly, due to better channel control, the channel region of MG MOSFETs can be left undoped or lightly doped. This leads to enhanced carrier mobility and lower random doping fluctuation (RDF) effects that are some added advantages of MG MOSFETs. Digital/analog circuits design with MOSFETs operating in subthreshold and weak/moderate inversion regime have gained wide interest these days due to their suitability for battery operated portable applications requiring ultra low power consumption, high gain with low/moderate frequency of operation. One of the major concerns for circuit design at this operation regime of device is its increased sensitivity to process, voltage and temperature variations. In addition, gate length scaling in nano-meter regime worsens various short channel effects (SCEs) that are posing serious threats to both digital and analog performance of the device. Considerable attention has been given for analyzing super threshold circuit behavior with progressive technology scaling, but no such attention has been given to subthreshold or weak/moderate inversion circuits, particularly using MG MOSFETs with circuit co-design techniques. Volume inversion in MG MOSFET is one of the important properties in this regard that has to be used effectively for performance improvement. The volume inverted carriers are confined at the center of the channel rather than at Si-SiO2 interface. This results in (i) Higher current due to great increase in number of minority carriers (ii) Reduction in surface scattering and interface defects (iii) Higher carrier mobility due to use of thick volume inversion as compared to narrow surface inversion and (iv) Higher transconductance. Secondly, for channel thickness between 5nm to 20nm, the volume inversion mobility of minority carriers are improved substantially at low temperature than at room temperature. These special features enhance the current iii drive, transconductance, subthreshold slope and speed of the device. Secondly, use of high-k gate dielectric material is beneficial in expanding design space due to possible use of thicker gate dielectric that can reduce the gate tunneling leakage while the device dimensions are scaled down in nano-meter regime. Nevertheless, fringe induced barrier lowering (FIBL) is fast becoming a major concern that can worsen SCEs, enhances off current and introduces threshold voltage roll–off because of loss of gate electrostatic control over the channel region. Third, Fin type FET (FinFET) has almost all advantages of MG MOSFETs in addition to lesser design related issues because of its self aligned gates. Providing sufficient underlap to the FinFET can enhance the digital performance because of variation in effective gate length in strong and weak inversion regime of operation of device. The analog performance of this kind of underlap FinFET is enhanced at subthreshold/weak inversion regime due to higher effective gate length. Nevertheless, introducing high-k spacer dielectric in underlap section of FinFET can enhance the digital performance because of gate fringe induced barrier lowering (GFIBL) effect. Dual-k spacer based underlap FinFET is another option for suppressing direct source to drain tunneling (DSDT) and short channel effects due to effective increase in gate fringing fields near gate edges of device via inner high-k spacer dielectric. This issue is addressed as first part of the work with detailed analysis of the impact of dual-k spacer on analog and short channel performance of device. The length of inner high-k spacer dielectric is optimized in terms of these performances. Suitable fin thickness is selected to account for the volume inversion effect too. From the study, we conclude that dual-k spacer formation in underlap FinFET is an attractive option in controlling DSDT, SCEs and improving analog figures of merit (FOM). The transconductance and output conductance improves in all extension lengths iv irrespective of doping gradient. Use of optimized inner high-k spacer length can compensate the increase in capacitance by transconductance improvement which can produce almost the same cutoff and maximum oscillation frequency as compared to low-k FinFET, in addition to a large increase in intrinsic gain. Transconductance-tocurrent ratio and early voltage are also observed to improve by formation of dual-k spacer in underlap FinFET. More so, pronounced effect of barrier modulation result in improved frequencies (fT and fmax) and intrinsic gain as the devices are scaled in nanometer regime. In the second part of the work, detailed analysis of the effect of variations on crucial device parameters like gate oxide thickness (Tox), fin width (Wfin), lateral straggle (Xj) of source drain doping profile etc., are carried out to formulate a guideline for dual-k spacer underlap FinFET design in analog domain. The process induced variations in these parameters are becoming more prominent with shrinking device dimensions causing negative impact on the inter device variability and, in turn, degrading the mismatch parameter. More so, the effect of alternative inner high-k spacer dielectric materials on analog performance of the device is studied in detail. It is shown that, for an optimum aspect ratio (fin height/fin width), the FOM of dual-k N/P-FinFETs are considerably higher and posses lesser variation to fin width, oxide thickness and S/D lateral straggle which, in turn, can improve the lithographic limitations at process level. Subsequently, the work has been extended to study the effect of spatial variations in critical transistor attributes, Tox and Xj of underlap FinFET, on single stage operational transconductance amplifier (OTA) performance. It is observed that, improved and variation less threshold voltage and mobility of dual-k FinFET are crucial in improving analog FOM like ADM, ACM and CMRR of the OTA. v The analog performance of the device can be enhanced at low temperature environment because of improved threshold voltage due to increase in fermi potential and improved carrier mobility due to volume inversion, subband splitting, reduced phonon scattering and enhanced velocity overshoot effect at liquid nitrogen range (≥77K). Therefore, in third part of our work, extensive study of low temperature operation of underlap FinFET is carried out. It is shown that, as the temperature is lowered to 100K, the percentage improvements in analog FOM of dual-k FinFET are enhanced further because of improvement in mobility and threshold voltage. Secondly, scaling down the gate length of dual-k FinFET to 10nm seems feasible at 100K temperature range, which can target AV0, fT and fmax of 44dB, 242GHz and 302GHz respectively. Fourth part of the work deals with development of analytical models for double gate underlap FinFET. The change in electric field line path between two different dielectric interfaces (εh and εl) of underlap section and its effect, is the part that have been modeled for the first time. Each underlap section has been divided into two parts low-k and high-k section. Modelling of inner high-k section is carried out by conformal mapping technique where as modeling of outer low-k section has been carried out by solving continuity equations in two different (low-k/high-k) dielectric interface and considering change in effective gate heights for the elliptical field lines at dielectric interface. It is shown that, the proposed model captures well the effect of inner high-k spacer on change in electric field lines at dielectric interface and its subsequent effect on potential profile of dual-k spacer based underlap FinFET. Furthermore, the model matches well with TCAD sentaurus device simulation results with variation in crucial device dimensions such as, gate oxide thickness, inner high-k spacer length and its dielectric constant. vi With lightly doped channel, the source/drain dopant species can intrude into the channel region when rapid thermal processing step following the high temperature annealing is performed to activate the dopant species. Therefore, final part of our work deals with generation of compact model for DG MOSFET that considers the effect of lateral straggle of source/drain gaussian profile. It has been observed that, increase in lateral straggle of source/drain gaussian profile facilitates propagation of lateral electric field which, in turn, lowers the threshold voltage and effective channel length of the device. These two effects will alter the current drive and change crucial parameters like transconductance, output conductance and, in turn, intrinsic gain of the device. Finally conclusions are drawn based on the findings of the research. Future scope of the work is also enumerated.