DESIGN AND ANALYSIS OF VERTICAL NANOWIRE CMOS DEVICES AND CIRCUITS

Abstract

The continued CMOS scaling has led to the need for introduction of 3-D transistors such as multigate FETs for technology nodes at 22 nm and below replacing planar MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Of these novel devices, the nanowire (NW) devices have minimum short channel effects (SCE) and allow thicker gate insulator thereby reducing the leakage currents in the device. Further, in NW device family, the Vertical Nanowire FETs (VNWFET) have additional strong advantage of occupying least silicon area due to vertical pillar structure and possibility of stacking devices vertically. This has driven numerous researchers to work on vertical nanowire devices and its circuits. Although there have been studies reporting device level fabrication results for VNW FETs, but due to fabrication challenges and large cost involved in developing technologies, accurate VNW CMOS circuit performance evaluation has not been well demonstrated and thoroughly investigated. The use of TCAD in VNW CMOS development is of high importance, as TCAD can help to reduce design cycles as well as provide critical insight into VNW CMOS behavior and key performance factors. At extremely scaled dimensions, the device and layout parasitics also start to dominate and are of high importance in evaluating circuit performance. The vertical device architecture has several issues like: newer/different kind of parasitic components such as contact overlapping nanowire tip, increased parasitic due to cylindrical structure and asymmetry due to differences in top/bottom electrodes contacts. Thus, the impact of parasitic and electrode asymmetry on device and circuit performance with scaling are important design issues. In this thesis, we investigate the performance of VNW CMOS and its design issues using well calibrated 3D TCAD simulations at 15 nm technology node as test vehicle. The important results are compared with corresponding FinFET/planar devices and circuits. Using well-calibrated process and device parameters the scaling performance of VNWFET device is performed with respect to channel length (LG), S/D extension length (S/Dext), gate overlap/underlap length (LOV), gate dielectric thickness (TOX) and nanowire diameter (DNW). The LG scaling study shows that the VNWFET devices can be easily scaled down to 15 nm with a thicker dielectric of 2 nm as opposed to less than 1 nm dielectric thickness required in planar MOSFETs. From, the S/Dext scaling and S/D asymmetry we find that device drive current can be increased by decreasing S/Dext and source as the bottom electrode has better performance. The optimum device structure parameters for 15 nm node are: LOV = 2 nm, TOX = 2 nm and DNW (NMOS/PMOS) = 10/15 nm. Also, it is shown that nth power law can be used to ii obtain device I-V characteristics matching to TCAD simulation results. Next, we develop models for parasitic series resistance and capacitance components which match well with simulation results. It is observed that gate to bottom electrode capacitance is a major contributor to device parasitic capacitance, while the contact and extension resistance are major contributors to device parasitic resistance. Further, the device performance with respect to LG, S/Dext and S/D asymmetry is explained with the help of modeled parasitic components. These parasitic models are later used in analyzing CMOS circuit performance. Finally, we study detailed digital and analog circuit performance of VNWFET CMOS. It is observed that due to better SCE, the VNWFET CMOS inverter voltage transfer characteristics (VTC) have sharper transition than planar MOSFET. Also, we note a gradient around the noise margin (NM) extraction point which is attributed to larger series resistance that can be minimized by reducing S/Dext. The CMOS inverter‘s dynamic performance is carried with respect to LG scaling and compared to reported FinFET and planar MOSFET inverters. It is found that VNWFET has the better delay, area and power performance when compared to planar or FinFET. The device S/D asymmetry leading to various possible CMOS layouts for a given circuit are investigated, we report new layout rule guidelines for VNWFET based circuit design. Further, it is shown that VNWFET based inverter delay can be improved by reducing S/Dext and by using device with source as bottom electrode provides best circuit performance. The CMOS inverter delay is modeled using the effective current method, which uses the parasitic capacitance model for delay prediction, and the delay model results match well with simulation results. This also explains the circuit performance with respect to S/Dext scaling and S/D asymmetry. Lastly, analog performance of VNWFET device is done and the intrinsic frequency response is compared to an equivalent FinFET. It is found that VNWFET has better gain, 3dB bandwidth and unity gain bandwidth (fT). Further, the impact of S/Dext length on common source (CS) amplifier is performed and it is seen that with lower source extension length the amplifier has better performance in terms of gain, 3dB bandwidth and fT. The overall results obtained in this study demonstrate that VNW CMOS has very high potential for use in CMOS based digital/analog circuits and offers best overall performance for CMOS technology nodes below 22 nm when compared to planar or FinFET. The study of digital/analog circuit design in this thesis highlight new circuit design methodologies and circuit layout rules, which addresses device asymmetry and parasitics. The parasitic models proposed through this work can be used to develop a compact SPICE model for VNWFET, with which circuit design and performance analysis on various standard cells, analog building blocks, SRAM cell and reliability study can be easily performed.