Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/14193
Title: ALL DIGITAL PHASE LOCKED LOOP WITH SUPPLY NOISE SUPPRESSION
Authors: Bairwan, Vipin
Keywords: design
minimum
jitter.
many
Issue Date: May-2016
Publisher: ELECTRICAL ENGINEERING IITR
Abstract: The purpose here is to design a Phase Locked Loop (PLL) because the design process is going to include topics from analog, digital, IC design, and control system theory. A phase locked loop (PLL) is a closed loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input reference signal. Phase locked loop is sensitive to both the frequency as well as phase of the input signal, automatically it has an ability to lead or lag the frequency of the feedback signal or reference signal in order to match the frequency and phase with minimum jitter. This property of phase locked loop made it unique hence used in many applications such as computers, radio, telecommunications and other applications where synchronization between receive and transmitter is required or we have to receive a signal even in the presence of noise. Here comparison between analog and digital phase locked loop is presented by comparing their lock time specifications then a digital phase locked loop is presented and implemented using VHDL that is very high speed integrated circuit hardware description language. Also to reduce the lock time and to make a phase locked loop suitable for high speed applications a proposed all digital phase locked loop is also presented
URI: http://hdl.handle.net/123456789/14193
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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