Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/14167
Title: TIMING MEASUREMENT OF MEMORIES USING LOW AREA, PROCESS IMMUNE TDCs
Authors: Rani, Shikha
Keywords: Time to Digital Converter (TDC),
Successive Approximation Register (SAR)
Analog to Digital Converter (ADC),
Digital to Analog Converter (DAC),
Comparator
Switched Capacitor Integrator
Issue Date: May-2016
Publisher: ELECTRONICS AND COMMUNICATION ENGINEERING IITR
Abstract: The access time of a memory which is one of the important performance parameters of memory design, is generally measured using time to digital converters (TDCs). This dissertation proposes a new analog type TDC architecture by exploiting a parasitic insensitive differential switched capacitor integrator which converts a time interval to be measured to voltage. The output voltage of the integrator is independent of the parasitic capacitances of the interconnects present between the two signal paths. The output voltage is then digitized using a 10-Bit Successive Approximation Register (SAR) type analog to digital converter (ADC). ADC employs a charge distribution type digital to analog converter (DAC). Various current and capacitor modes are provided to vary the measurement range and resolution of time measurement according to the accuracy required. The differential current given as input to the integrator is generated using a bandgap reference voltage source. The major advantage of the proposed design is that it can measure time interval ranging from 1ps to 10ns for a power supply of 1V, 0.9V and 0.8V which shows the efficacy of the technique across supply voltage. The bandgap reference source used to generate current always operates at a power supply of 1.8V. The minimum time resolution that can be achieved is 3ps for a measurement range of 200ps. It is dependent on the LSB of the ADC used. The maximum operating frequency at which the design can measure the time interval accurately at a power supply of 1V is 20MHz. It decreases with the reduction in power supply. The proposed design is simulated and verified in using the 28nm UTBB-FDSOI Technology of STMicroelectronics.
URI: http://hdl.handle.net/123456789/14167
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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