PERFORMANCE ENHANCEMENT OF MULTILEVEL INVERTER FOR INDUCTION MOTOR DRIVE

Abstract

Conversion from electrical energy to mechanical energy is an important process in modern industrial civilization and it is done by means of electrical machines. About half of the electrical energy generated in a developed country is ultimately consumed by electric motors, of which 90% are induction motors as they are simple, rugged and cheap. The rapid development of power electronic devices and converter technologies in the last few decades has made possible to develop energy efficient adjustable speed induction motor drives. The conventional two-level voltage source inverters (VSIs) are widely used in induction motor drive applications due to the simple structure, control, reliability as well as cheaper parts. In recent years, industries have begun to use high power equipment, which now are at megawatt levels. In high power and high performance drive applications, two-level VSIs suffers from problems like high dv/dt, higher switching loss, poor power quality, higher common-mode voltages and electromagnetic interference (EMI). Adjustable speed drives in megawatt range are usually connected to medium-voltage network due to restriction on current rating at low-voltage, therefore to connect the conventional two-level VSI with medium-voltage network several switching devices are to be connected in series. All the series connected switching devices should have accurate static and dynamic voltage sharing circuit which is not practically possible. Multilevel inverter (MLI) approach, on the other hand offers low dv/dt stress, good power quality, low switching loss, high voltage capability and good electro-magnetic compatibility (EMC) even at high power applications. Use of several levels of DC-voltage enables MLI to achieve better quality output voltages at low switching frequency. MLI topologies require more device count, but they are modular in structure and compact in size as they require reduced size output filter and transformer or none of them. Due to above features multilevel inverters emerge as an attractive solution for high power and high performance medium-voltage induction motor drives. Induction motors used in electric drives are either delta or star connected with three terminals and the motors are fed using two-level VSIs. In open-end winding induction motor, this delta or star connection is opened and the motor now has six terminals. The performance equivalent to 3-level inverter can be obtained by feeding these six terminals of open-end winding induction motor from both sides using two three-phase two-level VSI. There are certain advantages of the open-end winding method, such as common-mode voltage reduction and increase in the voltage transfer ratio. The multilevel inverter topologies proposed in the thesis uses this dual inverter fed open-end winding configuration for the induction motor. The present work is carried out to improve the performance of MLI for induction motor drive with simplified modelling, control and implementation. Problems associated with ii conventional two-level voltage source PWM (Pulse Width Modulation) inverter fed induction motor drives are addressed first. Their possible solutions and recent trends are discussed. Different MLIs topologies along with their features, technical challenges, applications, historical developments and research gaps are discussed. A comprehensive literature survey on MLI including various MLI topologies, diverse modulation and control schemes for induction motor are given in detail. MLI for induction motor drive is designed, developed and investigated. In the literature, it has been shown that an open-end winding induction motor drive fed with two-level VSI inverters produce phase voltage waveforms and voltage space vector locations similar to a conventional 3-level inverter. This dual two-level (D2L) configuration is taken as the first investigative object. A mathematical model of the squirrel cage open-end stator winding induction motor in stationary reference is developed along with switching function based D2L inverter model. The carrier based space vector pulse width modulation (SVPWM) scheme is used to generate the control pulses for switching devices. To investigate the performance of SVPWM based D2L inverter scheme for open-end induction motor drive under steady-state and dynamic conditions simulation study is carried out in MATLAB/Simulink environment. The developed motor model is operated in constant V/f mode under no-load condition covering the entire range of modulation. Various simulation results are obtained and analyzed for performance evaluation. A 5-level inverter configuration based on conventional 2-level inverters is selected as a second investigative object. The open-end winding induction motor is fed by 3-level inverter from one end and the other end is fed by two-level inverter. The combined effect of these two inverters generates five levels as -VDC/4, 0, +VDC/4, +VDC/2 and +3VDC/4, where VDC is the equivalent DC link voltage of the conventional two-level inverter fed induction motor drive. The 3-level inverter is realized by cascading two conventional two-level inverters. All three conventional two-level inverters are powered by isolated DC sources. This scheme uses asymmetrical DC link voltages to generate five levels in phase voltage of induction motor. A total of 512 space vector combinations are possible with this configuration which are distributed over 61 space vector locations. It has been shown that the same 5-level inverter circuit can produce six levels as -VDC/5, 0, +VDC/5, +2VDC/5, +3VDC/5 and +4VDC/5 by selecting a proper ratio of DC link voltages of individual two-level inverters. A switching function based mathematical model is developed and simulated with MATLAB/Simulink. The 5-level inverter performance is evaluated in MATLAB by running a 1.5 kW open-end winding induction motor model at no-load in V/f control mode. In the simulation results, it is found that the adopted scheme generates the voltage levels similar to conventional 5-level inverters. iii To generate high resolution voltage space vectors with reduced number of components for an open-end winding induction motor, a 9-level inverter scheme is proposed. The 9-level inverter operation is realized by feeding both ends of the open-end winding by two 3-level inverters with asymmetrical DC link voltage. These 3-level inverters are realized by cascading two 2-level inverters. The total DC link voltage VDC is divided into two 3-level inverters in the ratio of 3VDC/4 and VDC/4. The proposed topology completely eliminates the requirement of clamping diodes and DC-link capacitors which are needed in the neutral point clamped (NPC) inverter. It also eliminates eighty four capacitors of rating VDC/8 which are required in case of 9-level FC inverter topology. Compared to the conventional cascade Hbridge topology, the proposed inverter requires less number of power supplies. The flow of triplen harmonic current through the switches and motor windings is not possible in the proposed scheme due to use of four isolated DC supply. A modified level shifted triangular carrier based SVPWM technique is used for the proposed drive system. The proposed PWM scheme is capable of ensuring a smooth changeover from the mode of two-level inversion to the 3-level, then 3-level to 4-level, then from 4-level to 5-level and so on up to 9-level inversion and vice versa. This feature reduces the switching losses at lower speed range. A switching function based mathematical model of the proposed drive system is developed and validated by detailed analytical results in MATLAB/Simulink environment. A hybrid 9-level inverter is another configuration proposed in the thesis to reduce the requirement of four isolated DC sources of two different voltage rating into two isolated DC sources of the same voltage rating. The proposed topology is realized by feeding one end of the open-end winding induction motor by 5-level hybrid inverter and the other end by conventional two-level inverter. The three phase hybrid 5-level inverter is realized by cascading a 3-level flying capacitor (FC) inverter with capacitor fed H-bridge in each phase. The capacitor voltages are maintained at desired voltage level for the entire modulation range and also during transient operation by making use of redundant switching states available for generating different voltage levels. The proposed topology is capable of operating as 5-level inverter at full load in case of failure of H-bridge by simply bypass the faulty H-bridge; this feature enhances the reliability drive of the system. The proposed topology is compared with conventional topology in terms of the number of components used. The proposed inverter requires thirty IGBTs whereas the conventional topologies NPC, FC and CHB topology based 9-level inverters require forty eight IGBTs. As compared to asymmetrical cascade H-bridge (ACHB) topology which requires six isolated DC supply of two different voltages rating the proposed topology needs only two isolated DC supplies of the same rating. The proposed topology requires only six capacitors out of which three are of voltage rating VDC/4 and three are of voltage rating VDC/8 on the other hand, conventional 9- level FC inverter requires eighty four capacitors of voltage rating VDC/8. The conventional iv NPC 9-level inverter requires 168 clamping diodes and eight capacitors of voltage rating VDC/8; this requirement is completely eliminated in the proposed hybrid 9-level inverter. In the proposed inverter semiconductor switching devices which operated at a higher DC voltage switch less, hence low switching frequency rating devices can be used. As both sides inverters are fed by isolated DC supply so zero sequence currents are inherently prevented because there is no path available to flow of these currents. In the proposed hybrid 9-level inverter switching devices which operate at higher voltage level switch less as compared to the switching devices which operate at lower voltage level in the entire range of linear modulation, this feature can lead to use of low switching frequency rating power semiconductor devices hence overall cost is reduced. A switching state based mathematical model is developed to realize 9-level inversion operation. The space vector location and available switching redundancy at different locations are discussed. The capacitors voltage balancing algorithm and performance of the drive is evaluated during steady state and transient state in MATLAB/Simulink environment by operating an open-end winding induction motor at no-load in constant V/f mode and results are presented. The third topology proposed in the present work is an eighteen-level inverter topology for open-end winding induction motor drive. In the proposed topology one end of the openend IM is fed by conventional two-level inverter, while the other end is connected to a ninelevel asymmetrical cascade H-bridge (ACHB) inverter. The proposed topology is capable of generating eighteen levels as -VDC, -12VDC/13, -11VDC/13 -10VDC/13, -9VDC/13, -8VDC/13, -7VDC/13, -6VDC/13, -5VDC/13, -4VDC/13, -3VDC/13, -2VDC/13, -VDC/13, 0, +VDC/13, +2VDC/13, +3VDC/13 and +4VDC/13. The proposed topology requires less number of components as compared to conventional multilevel inverter (MLI) topology. An interesting feature of the proposed topology is that, it can operate in nine-level mode by connecting the motor winding in star in case of failure of the two-level inverter. Similarly, if the fault occurs in ACHB inverter the proposed inverter can operate in two-level mode. Thus, the reliability of the system is improved. Exhaustive simulation study is carried out to evaluate the performance of proposed inverter for the entire modulation range and results are presented. In this thesis extensive simulation study is carried out on D2L inverter, 5-level inverter, 9-level inverter, hybrid 9-level inverter and 18-level inverter for an induction motor with openend windings. In order to validate the simulation results, downscaled prototypes of following topologies are developed in the laboratory and experimentation is carried out: Topology-1: 5-Level Inverter for open-end IMD Topology-2: 9-Level Inverter for open-end IMD Topology-3: Hybrid 9-Level Inverter for open-end IMD The system hardware of these prototypes is developed in three stages: v • Implementation of power circuit • Implementation of control circuit • Measurement of system parameters The inverter circuits of all three topologies are developed using IGBTs (IRG4PH40KD). RT-Lab from Opal-RT Technologies is used as real-time hardware-in-loop controller to generate gate pulses for IGBTs in real-time. The different hardware circuits which are required for the proper operation of experimental setup such as driver circuit, isolation and dead-band circuits, voltage and current sensor circuits are designed, developed and interfaced with RT-Lab real time controller. In simulation studies of aforementioned topologies, the total DC link voltage (VDC) of 600V was selected, but due to the practical constraints total DC-link voltage of 200V is used for experimental investigations. An open-end winding induction motor of 1.5kW, 415V, 50Hz, 4pole is used as load and operated at no-load with constant V/f control. As the experimentation is carried out at reduced voltage, for validating the experimental results, the simulation study at reduced voltage is also carried out. The experimental and simulation results are matching to each other. The multilevel inverter topologies presented in this thesis are particularly suitable for high power drive applications such as an electric vehicle, traction, etc. Although all the proposed schemes are experimentally tested and validated on downscaled laboratory prototypes, but the proposed topologies, SVPWM technique and V/f control scheme are general in nature and can be easily applied to high power applications induction motor drive