1. Shodhbhagirathi @ IITR
  2. ELECTRICAL ENGINEERING
  3. MASTERS' THESES (Electrical Engg)
Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13600
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dc.contributor.authorKumar, Brajendra-
dc.date.accessioned2014-12-08T07:15:50Z-
dc.date.available2014-12-08T07:15:50Z-
dc.date.issued1999-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/13600-
dc.guideSingh, S. N.-
dc.guideGupta, H. O.-
dc.description.abstractThis dissertation work describe WLS state estimation algorithm, decomposition approach of state estimation, Bad data detection and topological error identification. The algorithm is tested on IEEE-14 bus system. The power Network is decomposed into number of blocks by identifying boundary buses and branches. The boundary buses are modelled as slack, bus for decomposition approach.en_US
dc.language.isoenen_US
dc.subjectELECTRICAL ENGINEERINGen_US
dc.subjectERROR IDENTIFICATIONen_US
dc.subjectSTATE ESTIMATIONen_US
dc.subjectPOWER SYSTEMen_US
dc.titleERROR IDENTIFICATION AND STATE ESTIMATION IN POWER SYSTEMen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number248306en_US
Appears in Collections:MASTERS' THESES (Electrical Engg)

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