Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13262
Authors: A, Suresh
Issue Date: 2006
Abstract: The area of the dissertation is TaskSKigration (to andfo between C(P?) and 1;confzgura6Ce System) with 1cconfigura6Ce System-on-Chip Arcfi itectures. To achieve tills Task Etigration the basic requirements are contributed 6y this dissertation. 'Tills dissertation import specif tally gives a detai(edd description of the "Soft ware/7(ardware Context Switch with R,cconfigura6Ce System-on-Chip Architectures" which is a crucia(part to achieve the endgoa(— "Task Migration': This dissertation is divided into three parts: The first part consists of learning VHDL and the usage of the design-flow associated with the Xilinx tools. The Xilinx tools namely Xilinx ISE and EDK (Embedded Design/Development Kit) consist of the complete design flow from VHDL to Bit stream generation (ISE) and complete system synthesis (SOC: System-ON-Chip) based on VHDL/C (EDK.). A communication module is implemented using these tools on Spartan-3 FPGA Kit and is manipulated for desired results: This part is dealt in the Hardware Part of this dissertation report. The second part consists of the evaluation of the connectivity between the CPU, memory and peripherals (partly self designed). The knowledge of the available connectivity is important for the communication between the VHDL code (implemented on the FPGA) and the Memory (On-Chip [Block Memory]/Off-chip). The communication is done by using the Bus Master which utilizes the IBM Core Connect Bus Infrastructure provided by the Xilinx Tools. The Virtex II Pro FPGA kit is used for this purpose. This part is dealt in the Hardware Part of this dissertation report. The Iast part consists of building up a rudimentary translation unit from LLVM/SSA to VHDL. The mapping of LLVM/SSA instructions to VHDL is to be divided into two parts. The first part consists of mapping the functional blocks to dataflow VHDL statements. In the first approach there may be an arbitrary constant number of instructions mapped per cycle. The second- part is to extract the existing control structure through the phi statements (related to SSA Form) which can also be described as scheduling of instructions for taking the complete advantage of the concurrent style of VHDL coding. Finally sequential C-code information stored in the form of Basic Blocks (in the Intermediate Representation of LLVM) is captured which is required for conversion into VHDL code to map each Basic Block to single VHDL process and necessary Glue Logic information is also captured to link these VHDL processes using C++ coding. Special care has to be taken with the memory accesses (as stated in second part). After these steps are completed, entire information is available for conversion process. There are a number of possible optimizations (beside the standard optimizations given by the compiler) which are implemented. One such optimization is: • create a cost estimation function which allows packing a variable number of instructions into one clock cycle i.e., scheduling of instructions within a Basic Block This part is dealt in the Software Part of this dissertation report. The abstract view of mapping of the C Code to VHDL Code is shown in the figure (next page):
Other Identifiers: M.Tech
Research Supervisor/ Guide: Verma, H. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

Files in This Item:
File Description SizeFormat 
G12775.pdf15.48 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.