Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13241
Title: IMPLEMENTATION OF NEURAL NETWORK BASED SVM ON FPGA FOR INDUCTION MOTOR DRIVE
Authors: Tatikonda, Subbarao
Keywords: ELECTRICAL ENGINEERING;NEURAL NETWORK BASED SVM;FPGA;INDUCTION MOTOR DRIVE
Issue Date: 2008
Abstract: The availability of high density Programmable Logic Devices (PLD) has opened an option of using concurrent processing ability to offset the limitations posed by the conventional DSP. Contemporary motor drives use programmable logic technology based dedicated motor control components, which can there be interface to DSP based controller or processor. Examples of such are reported includes architectures for current control, Space vector Pulse Width Modulation (SVPWM). A better solution for this can be obtained by implementing the control algorithm in neural networks. Implementation of neural networks on FPGA will take the advantage in parallel processing. A neural network based SVM can further increase the switching frequency, particularly when implemented on an application specific integrated circuit chip. Parallelism, modularity and dynamic adaptation are three computational characteristics typically associated with ANNs. FPGA-based reconfigurable computing architectures are well suited to implement ANNs. The purpose of this work is to show the advantage of the ANN as mentioned above. Controlling the speed of the induction machine using neural network based space vector pulse width modulation on field programmable gate arrays. Initial work is to design neural networks and choose the optimal network for the application. Transfer function should be selected in such a way that it could be the best fit for the FPGA. Test data has to be generated using the mathematical model of the system in Matlab. Important phase of the work is in designing the optimal network on FPGA which consumes the minimum resources. Theta is given as input to the neural network the outputs are the turn on time of the upper switches in phase A, B, C. Design of the timer and dead time blocks are the important factor in optimizing the resources by an efficient algorithms. IGBT based ASI PM is used for voltage source inverter to supply three phase voltage for the induction machine. Threshold voltage level of IGBT at room temperature is 3.5 to 5 volts. The pulses coming from FPGA are of 3.3 volts, these signals could not drive the IGBT. So a level converter circuit is designed using LM339 to increase the voltage level from 3.3 to 5. ii Neural network based space vector pulse width modulation find no limitation in terms of the switching frequency. The speed measurement block is designed to obtain the pulses from the speed encoder and to decode the pulses to the speed of the machine. The output voltage and currents total harmonic distortion is analyzed and found to be good for given operating conditions. iii
URI: http://hdl.handle.net/123456789/13241
Other Identifiers: M.Tech
Research Supervisor/ Guide: Agarwal, Pramoad
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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