Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13221
Title: IMPLEMENTATION OF IEEE 1451.2 COMPLIANT STIM
Authors: Marathe, Maheswar
Keywords: ELECTRICAL ENGINEERING;IEEE 1451.2 COMPLIANT STIM;SMART SENSOR NETWORK;SENSOR TECHNOLOGY
Issue Date: 2008
Abstract: A smart sensor network plays an important role in distributed measurement and control system, and there are over 60 networking protocols from which a network developer can chose. So transducer manufacturers and sensor users have been facing with the challenge of deciding which of the different available field bus technologies and device networks to implement. Fortunately, the IEEE 1451family of standards was issued to address the problems due to these complexities to the comfort of transducer manufacturers and sensor users[ 1]. The standards were first proposed in September 1993, by NIST and the IEEE's Technical Committee on Sensor Technology of the Instrumentation and Measurement Society. The IEEE 1451 standards offer manufacturers a true network independent standard for device connection, and simplify the creation of the network capable smart sensors over a network independent system. This family of standards are IEEE1451.1, IEEE1451.2, IEEEE1451.3, IEEE1451.4, IEEE 1451.5 and IEEE 1451.6. A prototype of the VHDL model of an IEEE 1451.2 standard compliant STIM (smart transducer interface module) with four channels has been successfully developed. The implemented four channels are analog sensor channel, digital smart sensor channel, actuator channel and switch channel respectively. The individual channel trigger logics, serial communication interface, memory block and channel register block were developed according to the standard and designed through VHDL and successfully implemented on FPGA. Basically the IEEE 1451.2 standard defines a common digital interface (TII) for all sensors and set of instructions to communicate with them. In addition to the interface functions, an electronic data sheet(TEDS) is included for sensor identification in order to ease the process of including new sensors in a network. All the digital modules of the STIM like main control, trigger logics, SPI etc. are designed, simulated and synthesized using the XILINX ISE 9.2i(see appendix B) and MODELSIMSE 6.Od software tool. This prototype has been implemented on FPGA. The target device is SPARTANs family XC3S 100E-5VQ 100 (see appendix C) which belongs to the SPARTAN-3E FPGA family. The main advantages of FPGA implementation for the STIM are system scalability and configurability, technology iv independence, enabling different implementations of the same system, integration of large systems and capability of integration of with different systems. The future scope of this work design of single chip USB sensors, design of smart biomedical network sensors having good accuracy for e-health monitoring, design of single chip network sensors with selected network interface, design of single chip multi-sensors with suitable network interface and Design of ASIC for IEE1451 single chip solution.
URI: http://hdl.handle.net/123456789/13221
Other Identifiers: M.Tech
Research Supervisor/ Guide: Varma, H. K.
Anand, R. S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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