Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13218
Title: FPGA IMPLEMENTATION OF REPROGRAMMABLE CONTROLLER FOR NCAP
Authors: Junuthula, Rathnakar Reddy
Keywords: ELECTRICAL ENGINEERING;FPGA IMPLEMENTATION;REPROGRAMMABLE CONTROLLER;NCAP
Issue Date: 2008
Abstract: Sensor networking is a fast growing technology. Networked transducers offer many advantages • to users. Today multiple control and sensor networking solutions are emerging, each requiring a separate and significant effort on the part of transducer manufacturers. It is too costly for transducer manufacturers to make unique smart transducers for each network on the market. Therefore a universally accepted transducer interface standard, the IEEE 1451 standard, has been evolved. The family of IEEE 1451 standards provides a common interface and enabling technology for the connectivity of transducers to microprocessors, control and field networks, and data acquisition and instrumentation systems. IEEE 1451.1 defines Network Capable Application Processor for connecting communication networks on one side, and sensors (or actuators) on the other. An Interface controller is required while connecting the NCAP to the communication network. This report presents the successful development of a reprogrammable interface controller that is important part of network capable application processor (NCAP). This NCAP features low redundancy of hardware because interfaces are implemented by software. The RIC is implemented on FPGA board so that NCAP get the ability to reconfigure types and parameters of the communication Interfaces according to meet user requirements so required flexibility of our NCAP can be achieved. The interface controller has been designed in VHDL, and targeted to Spartan 3E FPGA kit. Important aspects of these tools are described in detail in various sections of the report. Design, simulation and FPGA implementation of a protocol controller for the Controller Area Network (CAN) 2.0A multi-master serial communication protocol are described. The design method of each functional block is also presented in the report as an experience of how to easily design digital systems to be reused in different applications, assuring its quality and reliability.
URI: http://hdl.handle.net/123456789/13218
Other Identifiers: M.Tech
Research Supervisor/ Guide: Varma, H. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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