LLVIVI COMPILER BACKEND FOR VHDL AND POWERPC AND APPLICATION TO DSP ALGORITHMS

Abstract

Hardware/Software (HW/SW) codesign of an application is a popular design method-ology employed to meet the performance needs under design costs and time-to-market constraints. It stands for the design of a system or application using both hardware and software components. The advantages of software based design are flexibility, low cost and less development time and the advantages of hardware based design are liability (backup) and performance. HW/SW codesign is employed to achieve an optimal system design taking the advantage of individual designs. HW/SW partitioning is a primary step of HW/SW codesign which involves split-ting of the application into hardware and software divisions based on the initial design constraints such as performance, costs and hardware area. Automatic HW/SW parti-tioning is the automatic identification and sectioning of the critical code segments of the application which are to be implemented in hardware. There are a few works which have already implemented automatic HW/SW partitioning using various tools and tech-niques, but the present partitioning work is based on Low Level Virtual Machine (LLVM) compiler framework and a novelty of its kind. The LLVM is a compiler infrastructure designed to support life-long program analysis and transformation for arbitrary programs. LLVM provides tools and libraries used to build compilers, optimizers, code generators and many other compiler related programs. The present work is aimed as an extension to the LLVM tool chain which automati-cally creates a HW/SW division of the input algorithm. The input algorithm is lowered by the LLVM compiler frontend into the language and target independent LLVM In-termediate Representation (LLVM IR) and the backend modules written, modify the LLVM IR to create the HW/SW partitioned output. The backend modules comprise a Binning Pass and a Selection Pass. The LLVM Pass is a set of classes used to analyze, transform or output the LLVM IR. The Binning Pass is an analyze pass which employs heuristics to gather data flow and control flow statistics of the input algorithm written in C/C++ programming languages and empirical feature analysis is done to decide the parts of the algorithm to be implemented in HW/SW and the partitioning decision is taken after the above analysis. The Selection Pass is.a transform pass created to partition the input algorithm into HW/SW sections. The Selection Pass exploits the features collected by the Binning Pass to partition the algorithm for implementation in HW/SW. It modifies the LLVM IR of the input algorithm by replacing the set of the instructions which are not to be executed by the curent backend with intrinsic function calls. The above mentioned intrinsic instructions are defined as extensions to the LLVM language to keep the control and dataflows of the algorithm intact and are inserted at each context computing switch. The Selection Pass generates the LLVM IR of the hardware and software sections. The hardware section is sent to the LLVM VHDL backend which. transforms the LLVM IR into a VHDL RTL representation. The software section is sent to the LLVM PowerPC backend which transforms the LLVM IR into a PowerPC assembly language output. The backends are adapted to process the above mentioned intrinsic instructions. The work is based on the existing C/C++ frontends, VHDL and PowerPC backends of the compiler. The above passes have been tested and validated using input algorithms from the Digital Signal Processing (DSP) domain.