FPGA BASED DESIGN OF ON-CHIP PERIPHERAL (OPB) BUS BRIDGES FOR MULTIMEDIA APPLICATIONS

Abstract

With the recent advancements in silicon densities it is now possible to integrate numerous functions onto a single silicon chip. With this increased density, the peripherals that were for-merly attached to the processor at the card level are now integrated onto the same chip as the processor. Even it is possible now that the chip may contain several processors. Now a days this technology is popularly known as System-on-Chip (SoC). As large numbers of peripherals are present on the single -chip, on—chip buses are required to connect peripherals and the processor. With this aim in mind on-chip peripheral bus (OPB) and Processor Local Bus (PLB) were designed to integrate the different components as a complete system. On-chip Peripheral Bus (OPB) and Processor Local Bus (PLB) have different functions to perform.OPB is used for connecting slower peripherals and PLB for connecting faster peripherals that operate almost at the same speed as that of the processor .For carrying out the transaction between slower and faster components attached to the different buses bridges are designed called PLB to OPB bridge and OPB to PLB bridge. 'Xilinx has designed a tool called Embedded Development Kit (EDK) 6.3 that eases the designing of the complete embedded system This dissertation uses this tool to design application. OPB, PLB and bus bridges have been used to carry out the connectivity of the peripherals and the processor. Virtex-II Pro FPGA, one of the most sophisticated - FPGA available till date is used to realize the design in real time. Virtex-II Pro-PCI Video Card has been used in this dissertation for implementing the Multimedia Application. Power PC that is embedded into the Virtex-II Pro FPGA has been used as processing unit of the embedded'design.PLB to OPB Bridge has been used to connect the multimedia application to the Power PC.These bridges acts as a link between devices connected to different buses. Xilinx design tool ISE 6.3 has been used to actually Place and Route the design on the Virtex-II Pro FPGA.