Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13147
Authors: Rai, Shashank Sharan
Issue Date: 2007
Abstract: Recently, Field Programmable Gate Array (FPGA) technology has become a promising and viable platform for the implementation of image and video processing algorithms. The special features available with today's FPGAs have allowed the digital technology to be used in many such applications. Image reconstruction is a problem that involves complex trigonometric calculations and is inherently serial in nature. A high-speed hardware implementation of Filtered backprojection algorithm can address the problem of real-time image reconstruction for various practical applications. Today most of the applications where image reconstruction is required are demanding for a real-time image processing facility. However, an inherent serial nature of the process makes it infeasible with a software implementation. Though the software implementation of an image-processing algorithm may be comparatively easy from the development point of view, an upper limit on the speed of the execution is imposed by the slow speed is imposed by the slow speed interfaces. In that case, even a very fast CPU is not able to deliver the desired performance. For such cases, a dedicated hardware implementation generally gives a better result. As images grow larger in size and depth, the software implementation of image processing algorithms becomes less useful. For a real-time system, a hardware implementation may provide a more useful solution. In the current work, a Xilinx Virtex II-Pro video board is being used to implement the algorithm. A novel approach is proposed for the implementation of Filtered backprojection algorithm, which combines filtering and backprojection processes on a single chip. Few advanced features of Xilinx Virtex device are used to design architecture for Filtered backprojection algorithm that is able to perform filtering and backprojection operations in parallel. A one dimensional FIR filter has been implemented for filtering the individual projections. Then a custom digital circuitry is implementing the backprojection part of the algorithm. The final goal of the work is to demonstrate the reconstructed images from their respective Radon transforms.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Gupta, Indu
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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