LOW o POWER EMBEDDED PROCESSOR DESIGN

Abstract

The presented work is exploring an application area of FPGA to develop independent System on Programmable Chip (SOPC) design. This work describes the implementation of 16-bit Low-Power Embedded Processor in FPGA chip, using VHDL programming at Altera Quartus II platform supported by Aldec Active HDL simulation environment. The design is targeted to make a feel of a 16-bit processor available in FPGA. Embedded processor is very well managed with 5 stage pipelined RISC architecture and supports a total of 27 instructions (all major instructions included). Full modular approach with clock and signal gating methodology is applied to achieve a low power design. Successful synthesis is done and design is downloaded in Altera Cyclone FPGA. Output along with internal states of the embedded processor can be seen on VGA monitor through the VGA port of Altera UP3 kit available with us in microprocessor and computer lab. Synthesis reports and Power analysis reports are also provided to verify the design implementation and power dissipation. The work focuses on the design methodology based on tools and techniques to capture the design and develop a Hardware Prototype of it. Like any other engineering design I tested my design consistently and made modifications throughout when a problem arose. I added new pipelines and remapped my diagram of the processor before I had the code fully working. Simulation is done using Aldec Active HDL simulation environment to perform functionality test of this code. Synthesis optimization tools were used to convert the chip design in to smaller and faster design. Lastly the synthesized design is verified and various synthesis reports are analyzed to evaluate and verify the performance of the designed chip.