IMPLEMENTATION OF FIR FILTER IN FPGA

Abstract

The Finite Impulse Response (FIR) filter is a digital filter widely used in Digital Signal Processing applications in various fields like imaging, instrumentation, communications, etc. Programmable digital signal processors (PDSPs) can be used in implementing the FIR filter. However, in realizing a large-order filter many complex computations are needed which affects the performance of the common digital signal processors in terms of speed, cost, flexibility, etc. Field-Programmable gate Array (FPGA) has become an extremely cost-effective means of off-loading computationally intensive digital signal processing algorithms to improve overall system performance. The FIR filter implementation in FPGA, utilizing the dedicated hardware resources can effectively achieve application-specific integrated circuit (ASIC)-like performance while reducing development time, cost and risks. In this thesis, an Eight-order low-pass FIR filter is implemented in FPGA. Two different known approaches in the filter theory are used in this implementation. Firstly,. Cascade Decomposition is considered which overcomes the coefficient-sensitivity problem prevalent in FIR Direct Structures. However, this approach requires more number of complex multiplications than the FIR Direct structures that limits the speed of operation in real-time. Secondly, Distributed Arithmetic approach in realizing a digital filter is considered. This approach gives a better performance than the common filter structures in terms of speed of operation, cost and power consumption in real-time. It replaces the uses of - complex multiplications by using Adders, Shift Registers and Look-Up Tables. The FIR filter is implemented in Virtex-2-Pro FPGA and simulated with the help of Xilinx ISE (Integrated Software Environment)..