Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/13025
Authors: Sharma, Lokesh
Issue Date: 2006
Abstract: Due to inherent limitations of Fixed-point representation, it is sometimes desirable to perform arithmetic operations in the floating-point format. Although an established standard for floating-point arithmetic operations exist, the growing demand for high-performance computing platforms has pushed the computing community to work upon new architectures and algorithms for floating point arithmetic operations. Performing the arithmetic operations on IEEE Floating-point numbers imposed challenges beyond the challenges of Fixed-Point arithmetic. These challenges particularly include the task of normalization and IEEE compliant rounding. For some time now the researchers have been working on use of FPGAs to solve the problem. The presented work is also exploring an application area of FPGA to develop independent System on Programmable Chip (SOPC) design. This work describes the implementation of Floating-point arithmetic unit in FPGA chip, using VHDL programming on Xilinx ISE 7.1 platform supported by Modelsim and Aldec Active HDL simulation environment. Besides implementing the addition, subtraction, multiplication, division, square root, and absolute unit, some other supporting units like general purpose registers, control registers, tag register, status register etc are also implemented to make it work in stand-alone mode. This feature also provides flexibility of writing programs to the end user. The input/output number format confirms IEEE-754 standard single precision real numbers. Internally, calculations are performed according to IEEE-754 standard double-extended precision real numbers (as incorporated in Intel Pentium4 processor). This inherited feature assists floating-point arithmetic unit in enhancing the accuracy. A special care has been taken through the tag word. The tag register checks the validity of number before performing a complex arithmetic computation and thereby saves clock cycles in case the data register is empty or contains zero, infinity or invalid number. I also iv implemented the normalization unit and all four possible rounding modes. In essence, this dissertation presents a well thought FPGA implementation of all the basic arithmetic operations and a successful attempt has been made to save silicon area and reduce overall latency. , An implementation of turbine efficiency measurement is presented, illustrating the use of Floating-point arithmetic unit. Simulation and Synthesis results of all sub-components within the FPU and the efficiency measurement are also presented.
Other Identifiers: M.Tech
Research Supervisor/ Guide: Anand, R. S.
Verma, H. K.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' THESES (Electrical Engg)

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