DESIGN OF 1.1mW 2.4GHZ CMOS LOW NOISE AMPLIFIER BASED ON 90nm TECHNOLOGY

Abstract

Wireless and mobile are two of the fastest growing microelectronics applications, and have an enormous impact on our daily lives. The design of low cost, low power transceivers has gained substantial significance due to these applications. This work presents a design methodology for CMOS LNA applicable for low power applications. To demonstrate design methodology a narrow-band source degenerated cascode LNA is designed and simulated in a standard 90nm CMOS process to operate in the 2.4 GHZ band. The LNA achieves a voltage gain of 20.6dB, Noise figure of 2.87dB and consuming 1.1 mW power from 1 V supply voltage. Simulation study has been done using Micro Wave Office. The main contributions of this work include: 1) the introduction of a design methodology for power-efficient source degenerated LNA;- 2) the collection of design graphs to facilitate the exploration of tradeoffs between LNA performance and power consumption.