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|Title:||2 BITS/STEP SAR ADC WITH SELF-COMPENSATING COMPARATOR|
|Authors:||Reddy, J. Ravinder|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING;COMPARATOR;SELF-COMPENSATING;LOW RESOLUTION|
|Abstract:||Now-a-days High speed, Low resolution ADCs are of utmost concern because of continues growth in demand of UWB appliances. As process scales down many traditional ADC architectures, mostly relying on analog feedback will not perform well in scaled process, necessitating a change in ADC architecture. ADC architecture used in current work is hybrid version of Flash ADC and SAR ADC which has an inherent advantage of reduced normalized conversion (conversion energy/No. bits) energy. This hybrid structure is expected to replace Flash ADC in the upcoming years. Another advantage of present architecture is that the output code conversion block is outside the SAR loop enhancing the speed of ADC. SAR loop delay is reduced, thereby increasing the speed, by optimizing each block that comes along the critical path. Various optimization techniques of each block have been studied and well suited method has been used in their implementation. Next a self-compensating comparator has been proposed. The proposed comparator uses a Novel method of `back-gate biasing' technique to reduce the offset of the comparator. Then the proposed comparator has been deployed in SAR ADC and evaluated its dynamic performance.|
|Research Supervisor/ Guide:||Dasgupta, Sadeb|
|Appears in Collections:||MASTERS' DISSERTATIONS (E & C)|
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