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|Title:||ULTRA-LOW POWER FLIP-FLOPS USING CLOCK GATING AND SINGLE PHASE QUASI-STATIC ENERGY RECOVERY LOGIC|
|Authors:||Kumbhare, Rohan Vijay|
|Keywords:||ELECTRONICS AND COMPUTER ENGINEERING;ULTRA-LOW;FLIP-FLOPS;CLOCK GATING|
|Abstract:||In this work, we considered circuit level techniques for low energy computation using the principles of adiabatic and clock gating technique. This work presents ultra low power clock gating adiabatic D flip-flop, SR flip-flop and JK flip-flop using single phase sinusoidal power clock adiabatic scheme. Proposed flip-flops are realized with clock gating and single phase Quasi-Static Energy Recovery Logic in TSMC 90nm CMOS technology. In the previously proposed QSERL, two phase sinusoidal power clocks were used that required overhead of multiple clock generator circuit. In this work, single phase QSERL is used to reduce loss in the circuit. The proposed clock gating technique works efficiently for adiabatic flip-flops during idle periods to reduce undesired dynamic power dissipation. All the simulations have been performed using 90nm CMOS technology CADENCE spectre simulator. The use of clock gating and adiabatic technique simultaneously saves power dissipation of around 80% over conventional static CMOS technique at 100MHz. The 4-bit shift register has been designed using proposed single phase QSERL D flip-flop and compared with the conventional static CMOS 4-bit shift register circuit. The clock gating QSERL shift register can save approximately 82% of power dissipation over conventional CMOS shift register at 100MHz.|
|Research Supervisor/ Guide:||Saxena, Ashok K.|
|Appears in Collections:||MASTERS' THESES (E & C)|
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