Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/12519
Title: I/O BUFFER. DESIGN WITH LOW NOISE AND RELIABLE CIRCUIT OPERATION
Authors: Biswas, Arnab Kumar
Keywords: ELECTRONICS AND COMPUTER ENGINEERING;CIRCUIT OPERATION;DESIGN WITH LOW NOISE;INTERCHIP COMMUNICATION
Issue Date: 2011
Abstract: As the scaling continues, core circuitry of a chip is becoming smaller and faster. Supply voltage is decreasing at the same time. But outside world voltage level is almost remains same. For properly and reliably chip working, the contribution of I/O circuits is becoming more important. Extensive literature survey has been done in this thesis on various issues of I/O circuit design especially UO buffers. Some specific problems have been identified and their solution by designing improved 1/0 buffers has been given in this thesis. New innovative I/O buffers improve the (a) Reliability, (b) Signal Integrity and (c) Interchip Communication Speed of the chip in a systems environment. In the end conclusion and direction of future work has been discussed. Interchip communication requires reliable transmitter as well as receiver. So a new fully bidirectional I/O buffer using 0.35μm CMOS technology is proposed. The proposed buffer solves the problem of gate oxide overstress. It can work with a wider range of voltages i.e. 0.6/0.9/1.2/1.5/1.8/2.5/3.3/5 V. For the first time, to the best of our knowledge 0.6V bidirectional buffer is being reported. In addition, a new innovative input receiver is proposed which uses less number of MOS transistors than which has been reported in literature till now. With the advancement of technology and continuous device scaling the effect of parasitic components is increasing tremendously. So the need to improve signal integrity was never so much severe than now. For this we propose a new output buffer with controllable output resistance, which is useful for output signal monitoring. This can be used to minimize the switching noise or ringing noise. We have also compared the results with a conventional buffer and showed that the new buffer is relatively superior. Continuous increase in the effect of parasitic components causes sudden changes in signal level. This necessitates the use of input receiver with high noise immunity which can give proper logic level to the internal core circuitry. So an input receiver with hysteresis characteristic which can work from 0.9V to 3.3V with high noise margin is proposed. It can be used as a wide voltage range Schmitt trigger also. At the same time reliable circuit operation and a better frequency of operation is ensured. This is the first time in our knowledge a wide voltage range Schmitt trigger is being reported.
URI: http://hdl.handle.net/123456789/12519
Other Identifiers: M.Tech
Research Supervisor/ Guide: Bulusu, A.
Dasgupta, S.
metadata.dc.type: M.Tech Dessertation
Appears in Collections:MASTERS' DISSERTATIONS (E & C)

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