Please use this identifier to cite or link to this item: http://hdl.handle.net/123456789/12430
Title: PROGRAMMING LOAD FLOW STUDIES USING SPARSITY TECHNIQUES
Authors: Suryanarayana, D.
Keywords: ELECTRICAL ENGINEERING
PROGRAMMING LOAD FLOW STUDIES
SPARSITY TECHNIQUES
RAPHSON METHOD
Issue Date: 1981
Abstract: The work presented in this work deals with application of sparsity techniques to load flaw studies. As the size of the system increases, it becomes increasingly difficult to accommodate the problem within the core memory of the computer and sparse matrix techniques canes to the aid of the load flew analyst to overcane the problem of memory size and these techniques are absolutely essential for studying large modern interconnected systems. The technique also considerably speeds up the execution, as operations involving zero-elements are avoided and thereby# finds application especially for on-line studies where execution time should be as small as possible. Chapter II deals with the review of the load flow calcu-lation methods and the equations on which the computations are based. In Chapter III the various sparsity techniques have been dealt with. Chapter IV describes the factorization me-thods which are generally applied and in detail deals with the bi. factorization method which has been used in this work. etailed description of the computer algorithms for both Gauss-Seidel and Newton-Raphson metod have been given in Chapter V. The flow charts are given in appendix. Chapter VI gives the details and data of the problems studies and results obtained. In this wart sparsity techniques have been applied to load flow solution both by Gauss-Seidal and by Newton-Raphson method. ..2.0 In the Newton-.Raphson method the techniques of bi-facto... rization has been applied. It is seen that the Gauss.-Seidal method requires a large number of :' ,iterations for getting the solution. The Newton. Raphson method takes very few iterations to get the solution. However for the smaller systems the execution time is more. The methods have been tested on a 5 bus, 8 bus and IEEE standard 57 bus and 118 bus systems. The computational work has been carried on DEC 2050 computer system of the Roorkee University and execution times referred in this work correspond to D 2050 system.
URI: http://hdl.handle.net/123456789/12430
Other Identifiers: M.Tech
Appears in Collections:MASTERS' DISSERTATIONS (Electrical Engg)

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