1. Shodhbhagirathi @ IITR
  2. ELECTRICAL ENGINEERING
  3. MASTERS' THESES (Electrical Engg)
Please use this identifier to cite or link to this item: http://localhost:8081/xmlui/handle/123456789/12351
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dc.contributor.authorGavane, Avinash Shridhar-
dc.date.accessioned2014-12-01T04:43:24Z-
dc.date.available2014-12-01T04:43:24Z-
dc.date.issued1977-
dc.identifierM.Techen_US
dc.identifier.urihttp://hdl.handle.net/123456789/12351-
dc.guideRaja, A. K.-
dc.guideMisra, K. B.-
dc.description.abstractHere the equipment 'FAULT TREE 3IMULATOR.' is developed. The priliminary informations like 1. Various Path Sets 2. Minimal Path Sets 3, Various Cut Sets 4. Minimal Out Sets which are necessary in the Fault Tree Analysis of system can be obtained from the equipment.en_US
dc.language.isoenen_US
dc.subjectELECTRICAL ENGINEERINGen_US
dc.subjectFAULT TREE SIMULATORen_US
dc.subjectFAULT TREE ANALYSISen_US
dc.subjectFAULT TREE SIMULATOR DEVELOPMENTen_US
dc.titleDEVELOPMENT OF FAULT TREE SIMULATORen_US
dc.typeM.Tech Dessertationen_US
dc.accession.number109809en_US
Appears in Collections:MASTERS' THESES (Electrical Engg)

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