ANALYSIS OF UNDERLAP FINFET PARASITIC CAPACITANCE FOR CIRCUIT DESIGNING

Abstract

The past few decades have seen evolution of the semiconductor technology driven by scaling of the transistors. With every technology generation, devices and circuits are expected to achieve higher performance, lower power consumption; and larger integration density. To design circuits using highly scaled technologies there is a need for technology aware circuit design that considers device architecture to achieve optimal design. FinFETs are most promising substitutes for replacing bulk CMOS in nano scale circuits due to their easy manufacturability, low leakage currents and lower short channel effects. The device characteristics and fabrication aspects of FinFETs have got considerable attention in the last half a decade. Some circuit design techniques have also been reported by different researchers, but efficient circuit designing using FinFETs is still a major challenge. FinFET circuits are facing some issues over CMOS circuits, like width quantization and higher parasitics. These need special attention to evaluate circuit prospects of FinFETs. In this work initially we have designed an inverter and latches using 2D underlap FinFET device to understand the impact of device parasitics. After this part of circuit designing, analysis of parasitic effects in a FinFET inverter has been carried out. Different variations of parasitic capacitance of a FinFET inverter with circuit parameters like load capacitance and input transition time are analyzed by using a multi-transistor equivalent circuit of an underlap FinFET device. We have shown simulai.ion results and extracted data to support our study. Impacts of these variations on the circuit performance have also been analyzed in terms of effective fan out values of a FinFET inverter. We have shown through results that these parasitic variations have adverse effects on the circuit performance and need to be modeled properly in order to have an efficient circuit design methodology using FinFETs