NANOSCALE FINFETS: DEVICE AND CIRCUIT DESIGN METHODOLOGY

Abstract

Double gate FinFET has emerged as one of the most promising device that can replace bulk MOSFET as we approach sub-45 nm technologies. In these devices, the short channel effects are reduced because of better gate control and the use of a thin and lightly doped channel. In this dissertation report, a detailed analysis of the various scaling issues pertaining to DG FinFETs has been carried out through 2D simulations using a state of the art device simulator. Underlap FinFET device is used in this work because of it's superior subthreshold leakage immunity than overlap FinFET devices. For analyzing circuit aspects of FinFET device, a Standard Cell consisting Inverter, NAND, NOR and SR Latch were simulated using mixed mode simulation with and without external parasitics. We observed that in combinational cells, impact of internal parasitics of the device is much more than that of interconnect parasitics. We propose an optimized FinFET device design, such that circuit performance is improved. The Source/Drain extension parameters that we consider are pad doping concentration, extension spacer dielectric constant, gate oxide thickness (t,,), asymmetric doping profile and asymmetric spacer dielectric constants on source-drain side (Ks Ext). We observed that by optimizing t0X, Ks E,, device performance can be further improved. The value of to much more than its ITRS projected value can be used. We show using simulation that applying asymmetric device design with source spacer of a high dielectric constant improves device performance significantly. iv