OPTIMAL DESIGN OF NANOSCALE STANDARD CELLS CONSIDERING PARASITICS

Abstract

Speed and area are two main concerns in the design of modern integrated circuits. With scaling of technology, size of devices reducing and most of the chip area in is covering by interconnects, also, effects of parasitics on circuit performance cannot be neglected any more. Designer in the industry today uses semicustom design because it takes less time to layout a big circuit. However, this requires a lot of man hours to develop a complete standard cell library with different drive strengths. In this work, we have developed a standard cell library which contains 44 cells of basic logic gates like NAND, NOR, NOT, BUFFER, D-latch/ FF, Half-Adder, MUX. We have done a full characterization of library and from this found out that how important is the role of interconnects with scaling of technology. All the library cells are layed-out using Virtuoso Layout Editor and characterization of all cells are done on Specter circuit simulator (Cadence EDA Tool). We observe that the impact of local interconnect is critical in determining the timing parameters of sequential circuits. In sequential system, the most basic storing circuit is a D-latch. We have devised a new methodology to design D-latch. We have evaluated our method and compared the performance with earlier methodology of designing D-latch is observed an improvement in speed and reduction in area of d-latch cell. We have shown that our methodology produces D-latches with a greater robustness with respect to charge injection on dynamic nodes